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Hardware architecture for matrix factorization in MIMO receivers

Cerato, Barbara ; Masera, Guido and Nilsson, Peter LU (2007) 17th ACM Great Lakes Symposium on VLSI (GLSVLSI), 2007 p.196-199
Abstract
This paper presents the hardware realization of the factorization algorithm required in a MIMO OFDM receiver to make the detection and decoding a non-orthogonal space-time code. Requirements of a real scenario represented by the standard IEEE 802.11n for WLAN have been analyzed and exploited to draw out the specifications of the proposed implementation. A very high throughput hardware realization has been obtained able to factorize 128 8x8 real channel matrices during the channel updating period of 28 &3956;s, with a final throughput of 4,63 millions of matrices processed per second. Synthesis results on both 0.13 &3956;m CMOS standard cell technology and FPGA compare favourably to previous implementations.
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author
; and
organization
publishing date
type
Chapter in Book/Report/Conference proceeding
publication status
published
subject
host publication
Proceedings of the 17th great lakes symposium on Great lakes symposium on VLSI
pages
196 - 199
conference name
17th ACM Great Lakes Symposium on VLSI (GLSVLSI), 2007
conference location
Stresa - Lago Maggiore, Italy
conference dates
2007-03-11 - 2007-03-13
external identifiers
  • scopus:34748888581
ISBN
978-1-59593-605-9
DOI
10.1145/1228784.1228835
language
English
LU publication?
yes
id
16a4c84c-13f9-4890-9099-ea78a2a2ba0e (old id 1033923)
date added to LUP
2016-04-04 14:39:34
date last changed
2022-04-24 06:24:37
@inproceedings{16a4c84c-13f9-4890-9099-ea78a2a2ba0e,
  abstract     = {{This paper presents the hardware realization of the factorization algorithm required in a MIMO OFDM receiver to make the detection and decoding a non-orthogonal space-time code. Requirements of a real scenario represented by the standard IEEE 802.11n for WLAN have been analyzed and exploited to draw out the specifications of the proposed implementation. A very high throughput hardware realization has been obtained able to factorize 128 8x8 real channel matrices during the channel updating period of 28 &3956;s, with a final throughput of 4,63 millions of matrices processed per second. Synthesis results on both 0.13 &3956;m CMOS standard cell technology and FPGA compare favourably to previous implementations.}},
  author       = {{Cerato, Barbara and Masera, Guido and Nilsson, Peter}},
  booktitle    = {{Proceedings of the 17th great lakes symposium on Great lakes symposium on VLSI}},
  isbn         = {{978-1-59593-605-9}},
  language     = {{eng}},
  pages        = {{196--199}},
  title        = {{Hardware architecture for matrix factorization in MIMO receivers}},
  url          = {{http://dx.doi.org/10.1145/1228784.1228835}},
  doi          = {{10.1145/1228784.1228835}},
  year         = {{2007}},
}