A 10-bit 5-MS/s successive approximation ADC cell used in a 70-MS/s ADC array in 1.2-um CMOS
(1994) In IEEE Journal of Solid-State Circuits 29(8). p.866-872- Abstract
- A 10-bit 5-MS/s successive approximation ADC cell and a 70-MS/s parallel ADC array based on this cell, designed and fabricated in a 1.2-?m CMOS process, are presented. The ADC cell was designed to have an input bandwidth of more than 35 MHz and a sampling time of 14 nS at a clock rate of 70 MHz. The parallel ADC array consists of 14 such cells which are timed in one clock cycle skew successively in order to obtain digitized data every clock cycle. A two-step principle based on unsymmetrical dual-capacitor charge-redistribution-coupling has been used. With the help of a reset function, the comparator presents a fast response to the successive comparison. Each successive approximation ADC cell occupies an area of 0.6 mm2 and the core of the... (More)
- A 10-bit 5-MS/s successive approximation ADC cell and a 70-MS/s parallel ADC array based on this cell, designed and fabricated in a 1.2-?m CMOS process, are presented. The ADC cell was designed to have an input bandwidth of more than 35 MHz and a sampling time of 14 nS at a clock rate of 70 MHz. The parallel ADC array consists of 14 such cells which are timed in one clock cycle skew successively in order to obtain digitized data every clock cycle. A two-step principle based on unsymmetrical dual-capacitor charge-redistribution-coupling has been used. With the help of a reset function, the comparator presents a fast response to the successive comparison. Each successive approximation ADC cell occupies an area of 0.6 mm2 and the core of the parallel ADC array occupies an area of 2.7×3.3 mm2. The power consumptions for the cell and the parallel ADC array are 18 mW and 267 mW respectively (Less)
Please use this url to cite or link to this publication:
https://lup.lub.lu.se/record/1049673
- author
- Yuan, Jiren LU and Svensson, Christer
- publishing date
- 1994
- type
- Contribution to journal
- publication status
- published
- subject
- keywords
- SA-ADC, time-interleaving, parallel ADC
- in
- IEEE Journal of Solid-State Circuits
- volume
- 29
- issue
- 8
- pages
- 866 - 872
- publisher
- IEEE - Institute of Electrical and Electronics Engineers Inc.
- external identifiers
-
- scopus:0028485154
- ISSN
- 0018-9200
- DOI
- 10.1109/4.297689
- language
- English
- LU publication?
- no
- id
- 00c5163d-0d4d-43e1-9ad1-b93eb0b35658 (old id 1049673)
- date added to LUP
- 2016-04-01 16:42:57
- date last changed
- 2021-06-13 04:38:50
@article{00c5163d-0d4d-43e1-9ad1-b93eb0b35658,
abstract = {{A 10-bit 5-MS/s successive approximation ADC cell and a 70-MS/s parallel ADC array based on this cell, designed and fabricated in a 1.2-?m CMOS process, are presented. The ADC cell was designed to have an input bandwidth of more than 35 MHz and a sampling time of 14 nS at a clock rate of 70 MHz. The parallel ADC array consists of 14 such cells which are timed in one clock cycle skew successively in order to obtain digitized data every clock cycle. A two-step principle based on unsymmetrical dual-capacitor charge-redistribution-coupling has been used. With the help of a reset function, the comparator presents a fast response to the successive comparison. Each successive approximation ADC cell occupies an area of 0.6 mm2 and the core of the parallel ADC array occupies an area of 2.7×3.3 mm2. The power consumptions for the cell and the parallel ADC array are 18 mW and 267 mW respectively}},
author = {{Yuan, Jiren and Svensson, Christer}},
issn = {{0018-9200}},
keywords = {{SA-ADC; time-interleaving; parallel ADC}},
language = {{eng}},
number = {{8}},
pages = {{866--872}},
publisher = {{IEEE - Institute of Electrical and Electronics Engineers Inc.}},
series = {{IEEE Journal of Solid-State Circuits}},
title = {{A 10-bit 5-MS/s successive approximation ADC cell used in a 70-MS/s ADC array in 1.2-um CMOS}},
url = {{http://dx.doi.org/10.1109/4.297689}},
doi = {{10.1109/4.297689}},
volume = {{29}},
year = {{1994}},
}