A Distributed Architecture to Check Global Properties for Post-Silicon Debug
Larsson, Erik LU
; Vermeulen, Bart
and Goossens, Kees
(2010)
IEEE European Test Symposium (ETS'10), 2010
- Abstract
- Post-silicon validation and debug, or ensuring that software executes correctly on the silicon of a multi-processor system-on-chip (MPSOC) is complicated, as it involves checking global properties that are distributed on the chip. In this paper we define an architecture to non-intrusively observe global properties at run time using distributed monitors. The architecture enables to perform actions when a property holds, such as stopping (part of) the system for inspection. We apply this architecture to the problem of software races that result in incorrect communication between concurrent tasks on different processors. In a case study, where we implemented monitors, event distribution, and instruments to stop communication between... (More)
- Post-silicon validation and debug, or ensuring that software executes correctly on the silicon of a multi-processor system-on-chip (MPSOC) is complicated, as it involves checking global properties that are distributed on the chip. In this paper we define an architecture to non-intrusively observe global properties at run time using distributed monitors. The architecture enables to perform actions when a property holds, such as stopping (part of) the system for inspection. We apply this architecture to the problem of software races that result in incorrect communication between concurrent tasks on different processors. In a case study, where we implemented monitors, event distribution, and instruments to stop communication between intellectual property (IP) blocks, we demonstrate that these races can be detected and classified as timing violations or as FIFO protocol violations. (Less)
Please use this url to cite or link to this publication:
https://lup.lub.lu.se/record/2340842
- author
- Larsson, Erik
LU
; Vermeulen, Bart
and Goossens, Kees
- publishing date
- 2010
- type
- Chapter in Book/Report/Conference proceeding
- publication status
- published
- subject
- host publication
- Test Symposium (ETS), 2010 15th IEEE European
- publisher
- IEEE - Institute of Electrical and Electronics Engineers Inc.
- conference name
- IEEE European Test Symposium (ETS'10), 2010
- conference location
- Prague, Czech Republic
- conference dates
- 2010-05-24 - 2010-05-28
- external identifiers
-
- scopus:78049278395
- ISBN
- 978-1-4244-5834-9
- language
- English
- LU publication?
- no
- id
- 3ee7178f-a415-4a7f-8a5c-d7092b029177 (old id 2340842)
- date added to LUP
- 2016-04-04 09:57:01
- date last changed
- 2022-01-29 19:32:02
@inproceedings{3ee7178f-a415-4a7f-8a5c-d7092b029177,
abstract = {{Post-silicon validation and debug, or ensuring that software executes correctly on the silicon of a multi-processor system-on-chip (MPSOC) is complicated, as it involves checking global properties that are distributed on the chip. In this paper we define an architecture to non-intrusively observe global properties at run time using distributed monitors. The architecture enables to perform actions when a property holds, such as stopping (part of) the system for inspection. We apply this architecture to the problem of software races that result in incorrect communication between concurrent tasks on different processors. In a case study, where we implemented monitors, event distribution, and instruments to stop communication between intellectual property (IP) blocks, we demonstrate that these races can be detected and classified as timing violations or as FIFO protocol violations.}},
author = {{Larsson, Erik and Vermeulen, Bart and Goossens, Kees}},
booktitle = {{Test Symposium (ETS), 2010 15th IEEE European}},
isbn = {{978-1-4244-5834-9}},
language = {{eng}},
publisher = {{IEEE - Institute of Electrical and Electronics Engineers Inc.}},
title = {{A Distributed Architecture to Check Global Properties for Post-Silicon Debug}},
year = {{2010}},
}