On Minimization of Peak Power for Scan Circuit during Test
Tudu, Jaynarayan T. ; Larsson, Erik LU
; Singh, Virendra
and Agrawal, Vishwani
(2009)
European Test Symposium, ETS 2009
p.25-30
- Abstract
- Scan circuit generally causes excessive switching activity compared to normal circuit operation. The higher switching activity in turn causes higher peak power supply current which results into supply voltage droop and eventually yield loss. This paper proposes an efficient methodology for test vector re-ordering to achieve minimum peak power supported by the given test vector set. The proposed methodology also minimizes average power under the minimum peak power constraint. A methodology to further reduce the peak power, below the minimum supported peak power, by inclusion of minimum additional vectors is also discussed. The paper defines the lower bound on peak power for a given test set. The results on several benchmarks shows that it... (More)
- Scan circuit generally causes excessive switching activity compared to normal circuit operation. The higher switching activity in turn causes higher peak power supply current which results into supply voltage droop and eventually yield loss. This paper proposes an efficient methodology for test vector re-ordering to achieve minimum peak power supported by the given test vector set. The proposed methodology also minimizes average power under the minimum peak power constraint. A methodology to further reduce the peak power, below the minimum supported peak power, by inclusion of minimum additional vectors is also discussed. The paper defines the lower bound on peak power for a given test set. The results on several benchmarks shows that it can reduce peak power by up to 27%. (Less)
Please use this url to cite or link to this publication:
https://lup.lub.lu.se/record/2340898
- author
- Tudu, Jaynarayan T.
; Larsson, Erik
LU
; Singh, Virendra
and Agrawal, Vishwani
- publishing date
- 2009
- type
- Chapter in Book/Report/Conference proceeding
- publication status
- published
- subject
- host publication
- 2009 14th IEEE European Test Symposium
- pages
- 25 - 30
- conference name
- European Test Symposium, ETS 2009
- conference location
- Sevilla, Spain
- conference dates
- 2009-05-25 - 2009-05-29
- external identifiers
-
- scopus:70449379920
- ISBN
- 978-0-7695-3703-0
- DOI
- 10.1109/ETS.2009.36
- language
- English
- LU publication?
- no
- id
- 9a055757-c5b4-4f98-bcfa-d0ef6f1c124f (old id 2340898)
- date added to LUP
- 2016-04-04 13:57:58
- date last changed
- 2022-03-01 00:41:10
@inproceedings{9a055757-c5b4-4f98-bcfa-d0ef6f1c124f,
abstract = {{Scan circuit generally causes excessive switching activity compared to normal circuit operation. The higher switching activity in turn causes higher peak power supply current which results into supply voltage droop and eventually yield loss. This paper proposes an efficient methodology for test vector re-ordering to achieve minimum peak power supported by the given test vector set. The proposed methodology also minimizes average power under the minimum peak power constraint. A methodology to further reduce the peak power, below the minimum supported peak power, by inclusion of minimum additional vectors is also discussed. The paper defines the lower bound on peak power for a given test set. The results on several benchmarks shows that it can reduce peak power by up to 27%.}},
author = {{Tudu, Jaynarayan T. and Larsson, Erik and Singh, Virendra and Agrawal, Vishwani}},
booktitle = {{2009 14th IEEE European Test Symposium}},
isbn = {{978-0-7695-3703-0}},
language = {{eng}},
pages = {{25--30}},
title = {{On Minimization of Peak Power for Scan Circuit during Test}},
url = {{http://dx.doi.org/10.1109/ETS.2009.36}},
doi = {{10.1109/ETS.2009.36}},
year = {{2009}},
}