Core-Level Expansion of Compressed Test Patterns
Larsson, Anders ; Zhang, Xin ; Larsson, Erik LU
and Chakrabarty, Krishnendu
(2008)
17th Asian Test Symposium ATS
p.277-277
- Abstract
- The increasing test-data volumes needed for the testing of system-on-chip (SOC) integrated circuits lead to long test-application times and high tester memory requirements. Efficient test planning and test-data compression are therefore needed. We present an analysis to highlight the fact that the impact of a test-data compression technique on test time and compression ratio are method-dependant as well as TAM-width dependant. This implies that for a given set of compression schemes, there is no compression scheme that is the optimal with respect to test time reduction and test-data compression at all TAM widths. We therefore propose a technique where we integrate core wrapper design, test architecture design and test scheduling with... (More)
- The increasing test-data volumes needed for the testing of system-on-chip (SOC) integrated circuits lead to long test-application times and high tester memory requirements. Efficient test planning and test-data compression are therefore needed. We present an analysis to highlight the fact that the impact of a test-data compression technique on test time and compression ratio are method-dependant as well as TAM-width dependant. This implies that for a given set of compression schemes, there is no compression scheme that is the optimal with respect to test time reduction and test-data compression at all TAM widths. We therefore propose a technique where we integrate core wrapper design, test architecture design and test scheduling with test-data compression technique selection for each core in order to minimize the SOC test-application time and the test-data volume. Experimental results for several SOCs crafted from industrial cores demonstrate that the proposed method leads to significant reduction in test-data volume and test time. (Less)
Please use this url to cite or link to this publication:
https://lup.lub.lu.se/record/2340963
- author
- Larsson, Anders
; Zhang, Xin
; Larsson, Erik
LU
and Chakrabarty, Krishnendu
- publishing date
- 2008
- type
- Chapter in Book/Report/Conference proceeding
- publication status
- published
- subject
- keywords
- integrated circuits, system-on-chip, testing, test-data compression, memory requirements, wrapper design, test-application time
- host publication
- [Host publication title missing]
- pages
- 277 - 277
- publisher
- IEEE - Institute of Electrical and Electronics Engineers Inc.
- conference name
- 17th Asian Test Symposium ATS
- conference dates
- 0001-01-02
- external identifiers
-
- scopus:49749098371
- language
- English
- LU publication?
- no
- id
- be52888c-e4ee-4fc7-94e2-773e03b6943f (old id 2340963)
- alternative location
- http://www.ida.liu.se/labs/eslab/publications/pap/db/anlar_ats08.pdf
- date added to LUP
- 2016-04-04 10:06:16
- date last changed
- 2022-03-31 08:21:41
@inproceedings{be52888c-e4ee-4fc7-94e2-773e03b6943f,
abstract = {{The increasing test-data volumes needed for the testing of system-on-chip (SOC) integrated circuits lead to long test-application times and high tester memory requirements. Efficient test planning and test-data compression are therefore needed. We present an analysis to highlight the fact that the impact of a test-data compression technique on test time and compression ratio are method-dependant as well as TAM-width dependant. This implies that for a given set of compression schemes, there is no compression scheme that is the optimal with respect to test time reduction and test-data compression at all TAM widths. We therefore propose a technique where we integrate core wrapper design, test architecture design and test scheduling with test-data compression technique selection for each core in order to minimize the SOC test-application time and the test-data volume. Experimental results for several SOCs crafted from industrial cores demonstrate that the proposed method leads to significant reduction in test-data volume and test time.}},
author = {{Larsson, Anders and Zhang, Xin and Larsson, Erik and Chakrabarty, Krishnendu}},
booktitle = {{[Host publication title missing]}},
keywords = {{integrated circuits; system-on-chip; testing; test-data compression; memory requirements; wrapper design; test-application time}},
language = {{eng}},
pages = {{277--277}},
publisher = {{IEEE - Institute of Electrical and Electronics Engineers Inc.}},
title = {{Core-Level Expansion of Compressed Test Patterns}},
url = {{http://www.ida.liu.se/labs/eslab/publications/pap/db/anlar_ats08.pdf}},
year = {{2008}},
}