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A Technique for Test Infrastructure Design and Test Scheduling

Larsson, Erik LU orcid and Peng, Zebo (2000) Design and Diagnostic of Electronic Circuits and Systems Workshop DDECS p.26-26
Abstract
We propose a technique for test scheduling and design of test bus infrastructure where test application time and test bus length and width are minimized while constraints on power consumption and test resources are considered. Our approach is suitable for repeated use in the design space exploration process due to its low computational cost. For the final design, we use simulated annealing to optimize the solution. Our technique has been implemented and experimental results show the efficiency of our approach.
Please use this url to cite or link to this publication:
author
and
publishing date
type
Chapter in Book/Report/Conference proceeding
publication status
published
subject
keywords
testing, simulated annealing, test scheduling, test bus infrastructure
host publication
[Host publication title missing]
pages
26 - 26
publisher
IEEE - Institute of Electrical and Electronics Engineers Inc.
conference name
Design and Diagnostic of Electronic Circuits and Systems Workshop DDECS
conference dates
0001-01-02
language
English
LU publication?
no
id
2c74fbe7-3112-454d-8f78-ed99a722447d (old id 2340973)
alternative location
http://www.ida.liu.se/labs/eslab/publications/pap/db/DDECS00.ps.gz
date added to LUP
2016-04-04 11:30:52
date last changed
2018-11-21 21:05:19
@inproceedings{2c74fbe7-3112-454d-8f78-ed99a722447d,
  abstract     = {{We propose a technique for test scheduling and design of test bus infrastructure where test application time and test bus length and width are minimized while constraints on power consumption and test resources are considered. Our approach is suitable for repeated use in the design space exploration process due to its low computational cost. For the final design, we use simulated annealing to optimize the solution. Our technique has been implemented and experimental results show the efficiency of our approach.}},
  author       = {{Larsson, Erik and Peng, Zebo}},
  booktitle    = {{[Host publication title missing]}},
  keywords     = {{testing; simulated annealing; test scheduling; test bus infrastructure}},
  language     = {{eng}},
  pages        = {{26--26}},
  publisher    = {{IEEE - Institute of Electrical and Electronics Engineers Inc.}},
  title        = {{A Technique for Test Infrastructure Design and Test Scheduling}},
  url          = {{http://www.ida.liu.se/labs/eslab/publications/pap/db/DDECS00.ps.gz}},
  year         = {{2000}},
}