An Integrated System-on-Chip Test Framework
Larsson, Erik LU
and Peng, Zebo
(2008)
p.439-454
- Abstract
- In this paper we propose a framework for the testing of system-on-chip (SOC), which includes a set of design algorithms to deal with test scheduling, test access mechanism design, test sets selection, test parallelization, and test resource placement. The approach minimizes the test application time and the cost of the test access mechanism while considering constraints on tests, power consumption and test resources. The main feature of our approach is that it provides an integrated design environment to treat several different tasks at the same time, which were traditionally dealt with as separate problems. Experimental results shows the efficiency and the usefulness of the proposed technique.
Please use this url to cite or link to this publication:
https://lup.lub.lu.se/record/2340976
- author
- Larsson, Erik
LU
and Peng, Zebo
- publishing date
- 2008
- type
- Chapter in Book/Report/Conference proceeding
- publication status
- published
- subject
- keywords
- testing, system-on-chip, SOC, framework, integrated testing
- host publication
- [Host publication title missing]
- pages
- 439 - 454
- publisher
- Springer
- external identifiers
-
- scopus:84895307459
- ISBN
- 978-1-4020-6487-6
- language
- English
- LU publication?
- no
- id
- ff83144a-1211-4d33-bb45-361ffe019539 (old id 2340976)
- alternative location
- http://www.springer.com/east/home?SGWID=5-102-22-173748414-0&changeHeader=true&SHORTCUT=www.springer.com/978-1-4020-6487-6
- date added to LUP
- 2016-04-04 10:58:16
- date last changed
- 2022-01-29 21:09:18
@inbook{ff83144a-1211-4d33-bb45-361ffe019539,
abstract = {{In this paper we propose a framework for the testing of system-on-chip (SOC), which includes a set of design algorithms to deal with test scheduling, test access mechanism design, test sets selection, test parallelization, and test resource placement. The approach minimizes the test application time and the cost of the test access mechanism while considering constraints on tests, power consumption and test resources. The main feature of our approach is that it provides an integrated design environment to treat several different tasks at the same time, which were traditionally dealt with as separate problems. Experimental results shows the efficiency and the usefulness of the proposed technique.}},
author = {{Larsson, Erik and Peng, Zebo}},
booktitle = {{[Host publication title missing]}},
isbn = {{978-1-4020-6487-6}},
keywords = {{testing; system-on-chip; SOC; framework; integrated testing}},
language = {{eng}},
pages = {{439--454}},
publisher = {{Springer}},
title = {{An Integrated System-on-Chip Test Framework}},
url = {{http://www.springer.com/east/home?SGWID=5-102-22-173748414-0&changeHeader=true&SHORTCUT=www.springer.com/978-1-4020-6487-6}},
year = {{2008}},
}