Test-Architecture Optimization and Test Scheduling for SOCs with Core-Level Expansion of Compressed Test Patterns
Larsson, Anders ; Larsson, Erik LU
; Chakrabarty, Krishnendu
; Eles, Petru Ion
and Peng, Zebo
(2008)
Design, Automation, and Test in Europe DATE 2008
p.188-193
- Abstract
- Theever-increasing test data volume for core-based system-on-chip(SOC) integrated circuits is resulting in high test times andexcessive tester memory requirements. To reduce both test time andtest data volume, we propose a technique for test-architectureoptimization and test scheduling that is based on core-levelexpansion of compressed test patterns. For each wrapped embeddedcore and its decompressor, we show that the test time does notdecrease monotonically with the width of test access mechanism(TAM) at the decompressor input. We optimize the wrapper anddecompressor designs for each core, as well as the TAM architectureand the test schedule at the SOC level. Experimental results forSOCs crafted from several industrial cores demonstrate... (More)
- Theever-increasing test data volume for core-based system-on-chip(SOC) integrated circuits is resulting in high test times andexcessive tester memory requirements. To reduce both test time andtest data volume, we propose a technique for test-architectureoptimization and test scheduling that is based on core-levelexpansion of compressed test patterns. For each wrapped embeddedcore and its decompressor, we show that the test time does notdecrease monotonically with the width of test access mechanism(TAM) at the decompressor input. We optimize the wrapper anddecompressor designs for each core, as well as the TAM architectureand the test schedule at the SOC level. Experimental results forSOCs crafted from several industrial cores demonstrate that theproposed method leads to significant reduction in test data volumeand test time, especially when compared to a method that does notrely on core-level decompression of patterns. (Less)
Please use this url to cite or link to this publication:
https://lup.lub.lu.se/record/2340979
- author
- Larsson, Anders
; Larsson, Erik
LU
; Chakrabarty, Krishnendu
; Eles, Petru Ion
and Peng, Zebo
- publishing date
- 2008
- type
- Chapter in Book/Report/Conference proceeding
- publication status
- published
- subject
- keywords
- testing, system-on-chip, test-architecture optimization, test scheduling, test patterns, compression, test access mechanism, TAM, SOC
- host publication
- [Host publication title missing]
- pages
- 188 - 193
- publisher
- IEEE - Institute of Electrical and Electronics Engineers Inc.
- conference name
- Design, Automation, and Test in Europe DATE 2008
- conference location
- Munich, Germany
- conference dates
- 2008-03-10 - 2008-03-14
- external identifiers
-
- scopus:49749098371
- ISBN
- 978-3-9810801-3-
- DOI
- 10.1109/DATE.2008.4484684
- language
- English
- LU publication?
- no
- id
- 64ba8c44-eb3e-4e2e-b302-eb0a535e843f (old id 2340979)
- date added to LUP
- 2016-04-04 10:26:42
- date last changed
- 2022-03-31 08:59:18
@inproceedings{64ba8c44-eb3e-4e2e-b302-eb0a535e843f,
abstract = {{Theever-increasing test data volume for core-based system-on-chip(SOC) integrated circuits is resulting in high test times andexcessive tester memory requirements. To reduce both test time andtest data volume, we propose a technique for test-architectureoptimization and test scheduling that is based on core-levelexpansion of compressed test patterns. For each wrapped embeddedcore and its decompressor, we show that the test time does notdecrease monotonically with the width of test access mechanism(TAM) at the decompressor input. We optimize the wrapper anddecompressor designs for each core, as well as the TAM architectureand the test schedule at the SOC level. Experimental results forSOCs crafted from several industrial cores demonstrate that theproposed method leads to significant reduction in test data volumeand test time, especially when compared to a method that does notrely on core-level decompression of patterns.}},
author = {{Larsson, Anders and Larsson, Erik and Chakrabarty, Krishnendu and Eles, Petru Ion and Peng, Zebo}},
booktitle = {{[Host publication title missing]}},
isbn = {{978-3-9810801-3-}},
keywords = {{testing; system-on-chip; test-architecture optimization; test scheduling; test patterns; compression; test access mechanism; TAM; SOC}},
language = {{eng}},
pages = {{188--193}},
publisher = {{IEEE - Institute of Electrical and Electronics Engineers Inc.}},
title = {{Test-Architecture Optimization and Test Scheduling for SOCs with Core-Level Expansion of Compressed Test Patterns}},
url = {{http://dx.doi.org/10.1109/DATE.2008.4484684}},
doi = {{10.1109/DATE.2008.4484684}},
year = {{2008}},
}