A Technique for Optimization of System-on-Chip Test Data Transportation
Larsson, Anders ; Larsson, Erik LU
; Eles, Petru Ion
and Peng, Zebo
(2004)
9th IEEE European Test Symposium, 2004
p.179-180
- Abstract
- We propose a Tabu-search-based technique for time-constrained SOC (System-on-Chip) test data transportation. The technique makes use of the existing bus structure, where the advantage is, compared to adding dedicated test buses, that no additional routing is needed. In order to speed up the testing and to fulfill the time constraint, we introduce a buffer at each core, which in combination with dividing tests into smaller packages allows concurrent application of tests on a sequential bus. Our technique minimizes the combined cost of the added buffers and the test control logic. We have implemented the technique, and experimental results indicate that it produces high quality results at low computational cost.
Please use this url to cite or link to this publication:
https://lup.lub.lu.se/record/2341156
- author
- Larsson, Anders
; Larsson, Erik
LU
; Eles, Petru Ion
and Peng, Zebo
- publishing date
- 2004
- type
- Contribution to conference
- publication status
- published
- subject
- keywords
- system-on-chip, data transportation, test control logic
- pages
- 179 - 180
- conference name
- 9th IEEE European Test Symposium, 2004
- conference location
- Corsica, France
- conference dates
- 2004-05-23 - 2004-05-26
- language
- English
- LU publication?
- no
- id
- c5b48721-4854-46e4-88e9-a7c5c95b59dd (old id 2341156)
- alternative location
- http://www.ida.liu.se/labs/eslab/publications/pap/db/ets04.pdf
- date added to LUP
- 2016-04-04 14:35:00
- date last changed
- 2018-11-21 21:21:08
@misc{c5b48721-4854-46e4-88e9-a7c5c95b59dd,
abstract = {{We propose a Tabu-search-based technique for time-constrained SOC (System-on-Chip) test data transportation. The technique makes use of the existing bus structure, where the advantage is, compared to adding dedicated test buses, that no additional routing is needed. In order to speed up the testing and to fulfill the time constraint, we introduce a buffer at each core, which in combination with dividing tests into smaller packages allows concurrent application of tests on a sequential bus. Our technique minimizes the combined cost of the added buffers and the test control logic. We have implemented the technique, and experimental results indicate that it produces high quality results at low computational cost.}},
author = {{Larsson, Anders and Larsson, Erik and Eles, Petru Ion and Peng, Zebo}},
keywords = {{system-on-chip; data transportation; test control logic}},
language = {{eng}},
pages = {{179--180}},
title = {{A Technique for Optimization of System-on-Chip Test Data Transportation}},
url = {{http://www.ida.liu.se/labs/eslab/publications/pap/db/ets04.pdf}},
year = {{2004}},
}