A 100-fJ/cycle Sub-VT Decimation Filter Chain in 65 nm CMOS
Sherazi, Syed Muhammad Yasser LU ; Nilsson, Peter LU ; Sjöland, Henrik LU
and Rodrigues, Joachim
LU
(2012)
IEEE International Conference on Electronics, Circuits, and Systems (ICECS), 2012
- Abstract
- Measurements of a sub-threshold (sub-VT) decimation
filter, composed of four half band digital (HBD) filters in
65 nm CMOS are presented. Different unfolded architectures are
analyzed and implemented to combat speed degradation. The
architectures are analyzed for throughput and energy efficiency
over several threshold options. Reliability in the sub-VT domain
is analyzed by Monte-Carlo simulations. The simulation results
are validated by measurements and demonstrate that low-power
standard threshold logic (LP-SVT) and different architectural
flavors are suitable for a low-power implementation. Silicon
measurements prove functionality down to 350mV... (More) - Measurements of a sub-threshold (sub-VT) decimation
filter, composed of four half band digital (HBD) filters in
65 nm CMOS are presented. Different unfolded architectures are
analyzed and implemented to combat speed degradation. The
architectures are analyzed for throughput and energy efficiency
over several threshold options. Reliability in the sub-VT domain
is analyzed by Monte-Carlo simulations. The simulation results
are validated by measurements and demonstrate that low-power
standard threshold logic (LP-SVT) and different architectural
flavors are suitable for a low-power implementation. Silicon
measurements prove functionality down to 350mV supply, with
a maximum clock frequency of 500 kHz, having an energy
dissipation of 102 fJ/cycle. (Less)
Please use this url to cite or link to this publication:
https://lup.lub.lu.se/record/3166941
- author
- Sherazi, Syed Muhammad Yasser
LU
; Nilsson, Peter
LU
; Sjöland, Henrik
LU
and Rodrigues, Joachim
LU
- organization
- publishing date
- 2012
- type
- Chapter in Book/Report/Conference proceeding
- publication status
- published
- subject
- keywords
- energy dissipation, measurements, sub-threshold, half band digital (HBD) filters, 65 nm CMOS, and architectures.
- host publication
- 19th IEEE International Conference on Electronics, Circuits, and Systems (ICECS 2012)
- publisher
- IEEE - Institute of Electrical and Electronics Engineers Inc.
- conference name
- IEEE International Conference on Electronics, Circuits, and Systems (ICECS), 2012
- conference location
- Seville, Spain
- conference dates
- 2012-12-09 - 2012-12-12
- external identifiers
-
- scopus:84874594273
- ISBN
- 978-1-4673-1261-5
- 978-1-4673-1261-5
- DOI
- 10.1109/ICECS.2012.6463654
- project
- EIT_UPD Wireless Communication for Ultra Portable Devices
- language
- English
- LU publication?
- yes
- id
- 735747da-31f6-49ad-85ba-ff05edd0a26e (old id 3166941)
- date added to LUP
- 2016-04-04 11:27:08
- date last changed
- 2024-02-11 21:55:14
@inproceedings{735747da-31f6-49ad-85ba-ff05edd0a26e,
abstract = {{Measurements of a sub-threshold (sub-VT) decimation<br/><br>
filter, composed of four half band digital (HBD) filters in<br/><br>
65 nm CMOS are presented. Different unfolded architectures are<br/><br>
analyzed and implemented to combat speed degradation. The<br/><br>
architectures are analyzed for throughput and energy efficiency<br/><br>
over several threshold options. Reliability in the sub-VT domain<br/><br>
is analyzed by Monte-Carlo simulations. The simulation results<br/><br>
are validated by measurements and demonstrate that low-power<br/><br>
standard threshold logic (LP-SVT) and different architectural<br/><br>
flavors are suitable for a low-power implementation. Silicon<br/><br>
measurements prove functionality down to 350mV supply, with<br/><br>
a maximum clock frequency of 500 kHz, having an energy<br/><br>
dissipation of 102 fJ/cycle.}},
author = {{Sherazi, Syed Muhammad Yasser and Nilsson, Peter and Sjöland, Henrik and Rodrigues, Joachim}},
booktitle = {{19th IEEE International Conference on Electronics, Circuits, and Systems (ICECS 2012)}},
isbn = {{978-1-4673-1261-5}},
keywords = {{energy dissipation; measurements; sub-threshold; half band digital (HBD) filters; 65 nm CMOS; and architectures.}},
language = {{eng}},
publisher = {{IEEE - Institute of Electrical and Electronics Engineers Inc.}},
title = {{A 100-fJ/cycle Sub-VT Decimation Filter Chain in 65 nm CMOS}},
url = {{http://dx.doi.org/10.1109/ICECS.2012.6463654}},
doi = {{10.1109/ICECS.2012.6463654}},
year = {{2012}},
}