Distributed Clocking and Clock Generation in Digital CMOS SoC ASICs

Abstract

With shrinking technologies and higher clock rates comes the possibility to transform multi chip implementations to a single System on Chip (SoC). Implementing clock distribution and limiting the power consumption becomes increasingly troublesome with increased clock rate and chip area. Therefore, designing large Systems on Chip makes it necessary to search for new implementation methods. In this thesis, problems related to clock distribution and power consumption on a digital SoC are addressed.



Five papers are presented that focus on implementation issues for SoC with multiple clock regions and multiple supply voltages.



Paper I presents a low power, high frequency, small area digitally controlled on-chip clock generator. The clock generator is designed and fabricated using a 350 nm technology and delivers up to 1.15 GHz at 3.3 V supply voltage. At 1.0 V supply voltage, it delivers up to 92 MHz while consuming 0.16 mW.



Paper II presents a fully integrated clock generator with behavior similar to a PLL. A free-running ring oscillator is used as internal clock and the output clock is generated using two counters. The clock generator is described in synthesizable VHDL-code and can therefore easily be implemented from standard cells found in any commercial CMOS standard cell library.



Paper III presents a fully integrated digitally controlled PLL used as a clock multiplying circuit. The PLL has no off-chip components and it is made from standard cells found in most digital standard cell libraries.



In paper IV, a hardware solution for assigning two supply voltages to a design divided into blocks is presented. The two supply voltages are optimized using an on-chip controller. The on-chip controller assigns one out of two supply voltages to each block. This defines a solution suitable for reconfigurable designs.



Paper V presents a low-complexity method to simplify communication between modules using uncorrelated clocks. A description in synthesizable VHDL-code including local clock generators makes the method portable between technologies.

• author: Olsson, Thomas
• supervisor: [unknown] [unknown]
• opponent: Prof Alvandpour, Atila, Linköping University
• organization: Department of Electrical and Information Technology
• publishing date: 2004
• type: Thesis
• publication status: published
• subject: Electrical Engineering, Electronic Engineering, Information Engineering
• keywords: Electrical engineering, Elektroteknik, dual supply voltage, clock generator, digital, VHDL, CMOS, low-power, Distributed clocking, PLL
• pages: 167 pages
• defense location: Room E:1406, E-building, Lund Institute of Technology.
• defense date: 2004-06-03 10:15:00
• language: English
• LU publication?: yes
• additional info: Article: T. Olsson, P. Nilsson, T. Meincke, A. Hemani, and M. Torkelson, “A Digitally Controlled Low-Power Clock Multiplier for Globally AsynchronousLocally Synchronous Designs,” in Proceedings of the IEEE International Symposium on Circuits and Systems, ISCAS 2000, Geneva, Switzerland, May 28-31 2000. Article: T. Olsson and P. Nilsson, “A Portable Digital Clock Generator for Digital Signal Processing Applications,” IEE Electronics Letters, vol. 39, no. 19, September 2003. Article: T. Olsson and P. Nilsson, “A Digitally Controlled PLL for SoC Applications,”IEEE Journal of Solid-State Circuits, vol. 39, no. 5, May 2004. Article: T. Olsson, P. ˚Astr¨om, and P. Nilsson, “Dual Supply-Voltage Scaling forReconfigurable SoCs,” in Proceedings of the IEEE International Symposiumon Circuits and Systems, ISCAS 2001, vol. 2, Sydney, Australia, May 6–9 2001. Article: T. Olsson and P. Nilsson, “A Low-Complexity Method for Distributed Clocking in Digital ASICs,” submitted to APASIC 2004, Tokyo, Japan,August 3–5 2004.
• id: 618978c2-1e22-4fc4-8c95-4d7da92c64a0 (old id 467120)
• date added to LUP: 2016-04-01 15:51:26
• date last changed: 2018-11-21 20:36:55