A Heterogeneous Reconfigurable Cell Array for MIMO Signal Processing
Zhang, Chenxin LU ; Liu, Liang LU
; Markovic, Dejan
and Öwall, Viktor
LU
(2015)
In IEEE Transactions on Circuits and Systems Part 1: Regular Papers
62(3).
p.733-742
- Abstract
- This paper presents a heterogeneous reconfigurable cell array, designed for high-throughput baseband processing of multiple-input multiple-output (MIMO) systems. To achieve high performance and energy efficiency while retaining high flexibility, the proposed architecture adopts heterogeneous and hierarchical resource deployments. Additionally, extensive vector computation enhancements and flexible memory access schemes are employed to better support MIMO signal processing. Implemented in a 65 nm CMOS technology, the cell array occupies 8.88 ${rm mm}^{2}$ core area and is capable of running at 500 MHz. For illustration, three computationally intensive blocks, namely channel estimation, channel matrix pre-processing, and hard-output data... (More)
- This paper presents a heterogeneous reconfigurable cell array, designed for high-throughput baseband processing of multiple-input multiple-output (MIMO) systems. To achieve high performance and energy efficiency while retaining high flexibility, the proposed architecture adopts heterogeneous and hierarchical resource deployments. Additionally, extensive vector computation enhancements and flexible memory access schemes are employed to better support MIMO signal processing. Implemented in a 65 nm CMOS technology, the cell array occupies 8.88 ${rm mm}^{2}$ core area and is capable of running at 500 MHz. For illustration, three computationally intensive blocks, namely channel estimation, channel matrix pre-processing, and hard-output data detection, of a 4 $times$ 4 MIMO processing chain in a 20 MHz 64-QAM 3GPP long term evolution advanced (LTE-A) downlink are mapped and processed in real-time. Implementation results report a maximum throughput of 367.88 Mb/s with 1.49 nJ/b energy consumption. Compared to state-of-the-art designs, the proposed solution outperforms programmable platforms by several orders of magnitude in energy efficiency, and achieves similar level of efficiency to that of ASICs. (Less)
Please use this url to cite or link to this publication:
https://lup.lub.lu.se/record/4857003
- author
- Zhang, Chenxin
LU
; Liu, Liang
LU
; Markovic, Dejan
and Öwall, Viktor
LU
- organization
- publishing date
- 2015
- type
- Contribution to journal
- publication status
- published
- subject
- in
- IEEE Transactions on Circuits and Systems Part 1: Regular Papers
- volume
- 62
- issue
- 3
- pages
- 733 - 742
- publisher
- IEEE - Institute of Electrical and Electronics Engineers Inc.
- external identifiers
-
- wos:000350799100014
- scopus:85027941542
- ISSN
- 1549-8328
- DOI
- 10.1109/TCSI.2014.2366812
- project
- EIT_SOS VINNOVA Industrial Excellence Center - System Design on Silicon
- language
- English
- LU publication?
- yes
- id
- 68b1d3f9-5b7c-4601-97c0-442d17f34596 (old id 4857003)
- date added to LUP
- 2016-04-01 10:20:41
- date last changed
- 2024-01-06 14:20:48
@article{68b1d3f9-5b7c-4601-97c0-442d17f34596,
abstract = {{This paper presents a heterogeneous reconfigurable cell array, designed for high-throughput baseband processing of multiple-input multiple-output (MIMO) systems. To achieve high performance and energy efficiency while retaining high flexibility, the proposed architecture adopts heterogeneous and hierarchical resource deployments. Additionally, extensive vector computation enhancements and flexible memory access schemes are employed to better support MIMO signal processing. Implemented in a 65 nm CMOS technology, the cell array occupies 8.88 ${rm mm}^{2}$ core area and is capable of running at 500 MHz. For illustration, three computationally intensive blocks, namely channel estimation, channel matrix pre-processing, and hard-output data detection, of a 4 $times$ 4 MIMO processing chain in a 20 MHz 64-QAM 3GPP long term evolution advanced (LTE-A) downlink are mapped and processed in real-time. Implementation results report a maximum throughput of 367.88 Mb/s with 1.49 nJ/b energy consumption. Compared to state-of-the-art designs, the proposed solution outperforms programmable platforms by several orders of magnitude in energy efficiency, and achieves similar level of efficiency to that of ASICs.}},
author = {{Zhang, Chenxin and Liu, Liang and Markovic, Dejan and Öwall, Viktor}},
issn = {{1549-8328}},
language = {{eng}},
number = {{3}},
pages = {{733--742}},
publisher = {{IEEE - Institute of Electrical and Electronics Engineers Inc.}},
series = {{IEEE Transactions on Circuits and Systems Part 1: Regular Papers}},
title = {{A Heterogeneous Reconfigurable Cell Array for MIMO Signal Processing}},
url = {{https://lup.lub.lu.se/search/files/1767130/5469512.pdf}},
doi = {{10.1109/TCSI.2014.2366812}},
volume = {{62}},
year = {{2015}},
}