Mapping streaming applications on multiprocessors with time-division-multiplexed network-on-chip
Mirza, Usman Mazhar LU ; Gruian, Flavius LU
and Kuchcinski, Krzysztof
LU
(2014)
In Computers & Electrical Engineering
40(8).
p.276-291
- Abstract
- Abstract As custom multicore architectures become more and more common for DSP applications, instruction selection and scheduling for such applications and architectures become important topics. In this paper, we explore the effects of defining the problem of finding an optimal instruction selection and scheduling as a constraint satisfaction problem (CSP). We incorporate methods based on sub-graph isomorphism and global constraints designed for scheduling. We experiment using several media applications on a custom architecture, a generic VLIW architecture and a RISC architecture, all three with several cores. Our results show that defining the problem with constraints gives flexibility in modeling, while state-of-the-art constraint... (More)
- Abstract As custom multicore architectures become more and more common for DSP applications, instruction selection and scheduling for such applications and architectures become important topics. In this paper, we explore the effects of defining the problem of finding an optimal instruction selection and scheduling as a constraint satisfaction problem (CSP). We incorporate methods based on sub-graph isomorphism and global constraints designed for scheduling. We experiment using several media applications on a custom architecture, a generic VLIW architecture and a RISC architecture, all three with several cores. Our results show that defining the problem with constraints gives flexibility in modeling, while state-of-the-art constraint solvers enable optimal solutions for large problems, hinting a new method for code generation. (Less)
Please use this url to cite or link to this publication:
https://lup.lub.lu.se/record/4864527
- author
- Mirza, Usman Mazhar
LU
; Gruian, Flavius
LU
and Kuchcinski, Krzysztof
LU
- organization
- publishing date
- 2014
- type
- Contribution to journal
- publication status
- published
- subject
- in
- Computers & Electrical Engineering
- volume
- 40
- issue
- 8
- pages
- 276 - 291
- publisher
- Elsevier
- external identifiers
-
- wos:000348015800024
- scopus:84916601072
- ISSN
- 1879-0755
- DOI
- 10.1016/j.compeleceng.2014.08.015
- project
- High Performance Embedded Computing
- language
- English
- LU publication?
- yes
- id
- dce883b0-15d0-4bed-98e5-458c1634ac4f (old id 4864527)
- date added to LUP
- 2016-04-01 10:19:18
- date last changed
- 2022-02-10 00:58:56
@article{dce883b0-15d0-4bed-98e5-458c1634ac4f,
abstract = {{Abstract As custom multicore architectures become more and more common for DSP applications, instruction selection and scheduling for such applications and architectures become important topics. In this paper, we explore the effects of defining the problem of finding an optimal instruction selection and scheduling as a constraint satisfaction problem (CSP). We incorporate methods based on sub-graph isomorphism and global constraints designed for scheduling. We experiment using several media applications on a custom architecture, a generic VLIW architecture and a RISC architecture, all three with several cores. Our results show that defining the problem with constraints gives flexibility in modeling, while state-of-the-art constraint solvers enable optimal solutions for large problems, hinting a new method for code generation.}},
author = {{Mirza, Usman Mazhar and Gruian, Flavius and Kuchcinski, Krzysztof}},
issn = {{1879-0755}},
language = {{eng}},
number = {{8}},
pages = {{276--291}},
publisher = {{Elsevier}},
series = {{Computers & Electrical Engineering}},
title = {{Mapping streaming applications on multiprocessors with time-division-multiplexed network-on-chip}},
url = {{http://dx.doi.org/10.1016/j.compeleceng.2014.08.015}},
doi = {{10.1016/j.compeleceng.2014.08.015}},
volume = {{40}},
year = {{2014}},
}