A 3.5-6.8GHz wide-bandwidth DTC-assisted fractional-N all-digital PLL with a MASH ΔΣ TDC for low in-band phase noise
(2016) 42nd European Solid-State Circuits Conference, ESSCIRC 2016 2016-October. p.209-212- Abstract
We present a digital-to-time converter (DTC)-assisted fractional-N wide-bandwidth all-digital PLL (ADPLL). It employs a MASH ΔΣ time-to-digital converter (TDC) to achieve low in-band phase noise, and a wide-tuning range digitally-controlled oscillator (DCO). Fabricated in 40nm CMOS, the ADPLL consumes 10.7 mW while outputting 1.73 to 3.38 GHz (after a ÷2 division) and achieves better than -109 dBc/Hz in-band phase noise and 420fsrms integrated jitter.
Please use this url to cite or link to this publication:
https://lup.lub.lu.se/record/5b90b4ee-5cbc-4f82-8206-4695273e4405
- author
- Wu, Ying ; Shahmohammadi, Mina ; Chen, Yue ; Lu, Ping LU and Staszewski, Robert Bogdan
- organization
- publishing date
- 2016-10-18
- type
- Chapter in Book/Report/Conference proceeding
- publication status
- published
- subject
- keywords
- All digital PLL, BBPD, DCO, DTC, MASH, noise shaping, TDC, wide-bandwidth, wide-tuning range
- host publication
- ESSCIRC 2016: 42nd European Solid-State Circuits Conference
- volume
- 2016-October
- article number
- 7598279
- pages
- 4 pages
- publisher
- IEEE Computer Society
- conference name
- 42nd European Solid-State Circuits Conference, ESSCIRC 2016
- conference location
- Lausanne, Switzerland
- conference dates
- 2016-09-12 - 2016-09-15
- external identifiers
-
- scopus:84994389243
- ISBN
- 9781509029723
- DOI
- 10.1109/ESSCIRC.2016.7598279
- language
- English
- LU publication?
- yes
- id
- 5b90b4ee-5cbc-4f82-8206-4695273e4405
- date added to LUP
- 2016-12-07 09:51:01
- date last changed
- 2022-03-01 17:49:00
@inproceedings{5b90b4ee-5cbc-4f82-8206-4695273e4405, abstract = {{<p>We present a digital-to-time converter (DTC)-assisted fractional-N wide-bandwidth all-digital PLL (ADPLL). It employs a MASH ΔΣ time-to-digital converter (TDC) to achieve low in-band phase noise, and a wide-tuning range digitally-controlled oscillator (DCO). Fabricated in 40nm CMOS, the ADPLL consumes 10.7 mW while outputting 1.73 to 3.38 GHz (after a ÷2 division) and achieves better than -109 dBc/Hz in-band phase noise and 420fs<sub>rms</sub> integrated jitter.</p>}}, author = {{Wu, Ying and Shahmohammadi, Mina and Chen, Yue and Lu, Ping and Staszewski, Robert Bogdan}}, booktitle = {{ESSCIRC 2016: 42nd European Solid-State Circuits Conference}}, isbn = {{9781509029723}}, keywords = {{All digital PLL; BBPD; DCO; DTC; MASH; noise shaping; TDC; wide-bandwidth; wide-tuning range}}, language = {{eng}}, month = {{10}}, pages = {{209--212}}, publisher = {{IEEE Computer Society}}, title = {{A 3.5-6.8GHz wide-bandwidth DTC-assisted fractional-N all-digital PLL with a MASH ΔΣ TDC for low in-band phase noise}}, url = {{http://dx.doi.org/10.1109/ESSCIRC.2016.7598279}}, doi = {{10.1109/ESSCIRC.2016.7598279}}, volume = {{2016-October}}, year = {{2016}}, }