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Balancing BlockRAM and distributed RAM

Fang, Wen Hai LU ; Johansson, Thomas LU orcid and Spaanenburg, Lambert LU (2005) Swedish System-on-Chip Conference (SSoCC'05)
Abstract
Xilinx FPGAs offer both Block SelectRAM and distributed RAM for embedded memory. To investigate the impact of utilizing such opportunities, some variations on the hardware implementation of a SNOW 2.0 stream cipher IP core have been designed. We find the ratio of throughput and effective slice usage to be close to 3.5. This allows a flexible trade-off between speed and area consumption, with a throughput between 7200 and 8000 Mbps and a slice usage between 900 and 2400 for Xilinx Virtex II and 4.
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author
; and
organization
publishing date
type
Chapter in Book/Report/Conference proceeding
publication status
published
subject
host publication
Proceedings SSoCC 2005
conference name
Swedish System-on-Chip Conference (SSoCC'05)
conference location
Tammsvik, Sweden
conference dates
2005-04-18 - 2005-04-19
language
English
LU publication?
yes
id
6984b24f-cd57-4a56-b113-15b314dc60af (old id 603797)
date added to LUP
2016-04-04 13:58:10
date last changed
2018-11-21 21:17:29
@inproceedings{6984b24f-cd57-4a56-b113-15b314dc60af,
  abstract     = {{Xilinx FPGAs offer both Block SelectRAM and distributed RAM for embedded memory. To investigate the impact of utilizing such opportunities, some variations on the hardware implementation of a SNOW 2.0 stream cipher IP core have been designed. We find the ratio of throughput and effective slice usage to be close to 3.5. This allows a flexible trade-off between speed and area consumption, with a throughput between 7200 and 8000 Mbps and a slice usage between 900 and 2400 for Xilinx Virtex II and 4.}},
  author       = {{Fang, Wen Hai and Johansson, Thomas and Spaanenburg, Lambert}},
  booktitle    = {{Proceedings SSoCC 2005}},
  language     = {{eng}},
  title        = {{Balancing BlockRAM and distributed RAM}},
  year         = {{2005}},
}