Skip to main content

Lund University Publications

LUND UNIVERSITY LIBRARIES

A non-feedback multiphase clock generator

Lixin, Yang LU ; Yijun, Zhou LU and Yuan, Jiren LU (2002) 2002 IEEE International Symposium on Circuits and Systems p.389-392
Abstract
This paper introduces the design of a new multiphase clock generator with no feedback loop. A single-stage direct interpolation architecture is proposed. A 1/4 frequency divider and a short-circuit current suppression interpolator are developed to achieve the precise interpolation. The circuit has been fabricated in a standard 0.35 μm, 3.3 V CMOS process. The multiphase clock generator can operate in a wide range of input clock frequencies from 500 MHz to 1.5 GHz
Please use this url to cite or link to this publication:
author
; and
organization
publishing date
type
Chapter in Book/Report/Conference proceeding
publication status
published
subject
keywords
no feedback loop, multiphase clock generator, single-stage direct interpolation architecture, 1/4 frequency divider, 500 MHz to 1.5 GHz, short-circuit current suppression interpolator, 0.35 micron, 3.3 V, input clock frequency range, CMOS process
host publication
2002 IEEE International Symposium on Circuits and Systems. Proceedings (Cat. No.02CH37353)
pages
389 - 392
publisher
IEEE - Institute of Electrical and Electronics Engineers Inc.
conference name
2002 IEEE International Symposium on Circuits and Systems
conference dates
2002-05-26 - 2002-05-29
external identifiers
  • wos:000186328300098
  • scopus:0036296186
ISBN
0-7803-7448-7
DOI
10.1109/ISCAS.2002.1010473
language
English
LU publication?
yes
id
3af9862a-a891-403b-acdb-eef80bc043ab (old id 610431)
date added to LUP
2016-04-04 11:45:01
date last changed
2022-04-24 01:07:32
@inproceedings{3af9862a-a891-403b-acdb-eef80bc043ab,
  abstract     = {{This paper introduces the design of a new multiphase clock generator with no feedback loop. A single-stage direct interpolation architecture is proposed. A 1/4 frequency divider and a short-circuit current suppression interpolator are developed to achieve the precise interpolation. The circuit has been fabricated in a standard 0.35 μm, 3.3 V CMOS process. The multiphase clock generator can operate in a wide range of input clock frequencies from 500 MHz to 1.5 GHz}},
  author       = {{Lixin, Yang and Yijun, Zhou and Yuan, Jiren}},
  booktitle    = {{2002 IEEE International Symposium on Circuits and Systems. Proceedings (Cat. No.02CH37353)}},
  isbn         = {{0-7803-7448-7}},
  keywords     = {{no feedback loop; multiphase clock generator; single-stage direct interpolation architecture; 1/4 frequency divider; 500 MHz to 1.5 GHz; short-circuit current suppression interpolator; 0.35 micron; 3.3 V; input clock frequency range; CMOS process}},
  language     = {{eng}},
  pages        = {{389--392}},
  publisher    = {{IEEE - Institute of Electrical and Electronics Engineers Inc.}},
  title        = {{A non-feedback multiphase clock generator}},
  url          = {{http://dx.doi.org/10.1109/ISCAS.2002.1010473}},
  doi          = {{10.1109/ISCAS.2002.1010473}},
  year         = {{2002}},
}