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A 65nm CMOS fraction-N digital PLL with shaped in-band phase noise

Mahmoud, Ahmed LU ; Andreani, Piero LU and Lu, Ping LU (2015) Nordic Circuits and Systems Conference (NORCAS): NORCHIP & International Symposium on System-on-Chip (SoC)
Abstract
A digital phase-locked loop (DPLL) which uses a high resolution 2-dimension gated-Vernier time-to-digital converter (TDC) is presented. The shaped Vernier quantization of TDC greatly improves the in-band phase noise. Also the 2-dimension structure makes DPLL be able to process large phase errors almost without the influence of latency time. Combined with a high figure-of-merit (FOM) class-D digitally controlled oscillator (DCO), the DPLL achieves -110dBc/Hz and -130dBc/Hz for in-band and 1MHz-offset phase noise, respectively, with carrier frequency of 3.5 GHz. The digital PLL is simulated in a 65nm CMOS process, consuming 11.2mW from a 1.0V supply.
Please use this url to cite or link to this publication:
author
; and
organization
publishing date
type
Chapter in Book/Report/Conference proceeding
publication status
published
subject
keywords
Vernier, gated, noise shaping, 2-dimension, DPLL, TDC, class-D
host publication
Nordic Circuits and Systems Conference (NORCAS): NORCHIP & International Symposium on System-on-Chip (SoC)
conference name
Nordic Circuits and Systems Conference (NORCAS): NORCHIP & International Symposium on System-on-Chip (SoC)
conference location
Oslo, Norway
conference dates
2015-10-26 - 2015-10-28
external identifiers
  • scopus:84963717972
ISBN
978-1-4673-6576-5
DOI
10.1109/NORCHIP.2015.7364356
language
English
LU publication?
yes
id
df7ec966-34fe-42ee-bace-bb463003d4ed
date added to LUP
2016-05-31 11:23:54
date last changed
2022-05-02 03:36:12
@inproceedings{df7ec966-34fe-42ee-bace-bb463003d4ed,
  abstract     = {{A digital phase-locked loop (DPLL) which uses a high resolution 2-dimension gated-Vernier time-to-digital converter (TDC) is presented. The shaped Vernier quantization of TDC greatly improves the in-band phase noise. Also the 2-dimension structure makes DPLL be able to process large phase errors almost without the influence of latency time. Combined with a high figure-of-merit (FOM) class-D digitally controlled oscillator (DCO), the DPLL achieves -110dBc/Hz and -130dBc/Hz for in-band and 1MHz-offset phase noise, respectively, with carrier frequency of 3.5 GHz. The digital PLL is simulated in a 65nm CMOS process, consuming 11.2mW from a 1.0V supply.}},
  author       = {{Mahmoud, Ahmed and Andreani, Piero and Lu, Ping}},
  booktitle    = {{Nordic Circuits and Systems Conference (NORCAS): NORCHIP & International Symposium on System-on-Chip (SoC)}},
  isbn         = {{978-1-4673-6576-5}},
  keywords     = {{Vernier; gated; noise shaping; 2-dimension; DPLL; TDC; class-D}},
  language     = {{eng}},
  title        = {{A 65nm CMOS fraction-N digital PLL with shaped in-band phase noise}},
  url          = {{http://dx.doi.org/10.1109/NORCHIP.2015.7364356}},
  doi          = {{10.1109/NORCHIP.2015.7364356}},
  year         = {{2015}},
}