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An OFDM Timing Synchronization ASIC

Johansson, Stefan; Nilsson, Martin LU and Nilsson, Peter LU (2000) 7th IEEE International Conference on Electronics, Circuits and Systems (ICECS’2K) In The 7th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2000. 1. p.324-327
Abstract
In this paper an OFDM timing synchronization ASIC is presented. The proposed synchronization unit can be used in any OFDM system. The algorithm is based on the correlation introduced by the cyclic prefix, which is exploited in the time domain where the time offset is estimated. Although the algorithm is too complex to be implemented on today's most powerful standard DSP, a hardware architecture that is optimized for the algorithm is implemented with moderate complexity. The unit contains 32 kbit RAM and 3000 gates. At the sample rate of 25 Msamples/s the power consumption is 16 mW, which is small for such a complex algorithm
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author
organization
publishing date
type
Chapter in Book/Report/Conference proceeding
publication status
published
subject
in
The 7th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2000.
volume
1
pages
324 - 327
conference name
7th IEEE International Conference on Electronics, Circuits and Systems (ICECS’2K)
external identifiers
  • Scopus:67650226339
ISBN
0-7803-6542-9
DOI
10.1109/ICECS.2000.911547
language
English
LU publication?
yes
id
a32614e2-f2d8-4fa6-bfd6-93ba516fe0a7 (old id 1034063)
date added to LUP
2008-02-26 14:45:58
date last changed
2016-10-13 05:03:31
@misc{a32614e2-f2d8-4fa6-bfd6-93ba516fe0a7,
  abstract     = {In this paper an OFDM timing synchronization ASIC is presented. The proposed synchronization unit can be used in any OFDM system. The algorithm is based on the correlation introduced by the cyclic prefix, which is exploited in the time domain where the time offset is estimated. Although the algorithm is too complex to be implemented on today's most powerful standard DSP, a hardware architecture that is optimized for the algorithm is implemented with moderate complexity. The unit contains 32 kbit RAM and 3000 gates. At the sample rate of 25 Msamples/s the power consumption is 16 mW, which is small for such a complex algorithm},
  author       = {Johansson, Stefan and Nilsson, Martin and Nilsson, Peter},
  isbn         = {0-7803-6542-9},
  language     = {eng},
  pages        = {324--327},
  series       = {The 7th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2000.},
  title        = {An OFDM Timing Synchronization ASIC},
  url          = {http://dx.doi.org/10.1109/ICECS.2000.911547},
  volume       = {1},
  year         = {2000},
}