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Globally Asynchronous Locally Synchronous Architecture for Large High-performance ASICs

Meincke, Thomas; Hemani, Ahmed; Kumar, Shashi; Öberg, Johnny; Olsson, Thomas LU ; Nilsson, Peter LU ; Lindqvist, Dan and Tenhunen, Hannu (1999) 1999 International Symposium on Circuits and Systems (ISCAS’99) In Proceedings of the 1999 IEEE International Symposium on Circuits and Systems, ISCAS '99. 2. p.512-515
Abstract
Clock nets are the major source of power consumption in large, high-performance ASICs and a design bottleneck when it comes to tolerable clock skew. A way to obviate the global clock net is to partition the design into large synchronous blocks each having its own clock. Data with other blocks is exchanged asynchronously using handshake signals. Adopting such a strategy requires a methodology that supports: 1) a partitioning method dividing a design into the number of synchronous blocks such that the gain due to global clock net removal exceeds the communication overhead and 2) synthesis of handshake protocols to implement the data transfer between synchronous blocks. We describe this methodology and present results of applying it to a... (More)
Clock nets are the major source of power consumption in large, high-performance ASICs and a design bottleneck when it comes to tolerable clock skew. A way to obviate the global clock net is to partition the design into large synchronous blocks each having its own clock. Data with other blocks is exchanged asynchronously using handshake signals. Adopting such a strategy requires a methodology that supports: 1) a partitioning method dividing a design into the number of synchronous blocks such that the gain due to global clock net removal exceeds the communication overhead and 2) synthesis of handshake protocols to implement the data transfer between synchronous blocks. We describe this methodology and present results of applying it to a realistic design done in 0.25 micron, ranging in operating frequencies from 20 MHz to 1 GHz. The results show that the net power savings compared to fully synchronous designs are on an average about 30% (Less)
Please use this url to cite or link to this publication:
author
organization
publishing date
type
Chapter in Book/Report/Conference proceeding
publication status
published
subject
in
Proceedings of the 1999 IEEE International Symposium on Circuits and Systems, ISCAS '99.
volume
2
pages
512 - 515
publisher
IEEE--Institute of Electrical and Electronics Engineers Inc.
conference name
1999 International Symposium on Circuits and Systems (ISCAS’99)
external identifiers
  • Scopus:0038791435
ISBN
0-7803-5471-0
DOI
10.1109/ISCAS.1999.780794
language
English
LU publication?
yes
id
aaec33d1-df3d-4569-977b-3f37066b54d1 (old id 1034090)
date added to LUP
2008-02-27 09:38:06
date last changed
2016-12-04 04:44:39
@misc{aaec33d1-df3d-4569-977b-3f37066b54d1,
  abstract     = {Clock nets are the major source of power consumption in large, high-performance ASICs and a design bottleneck when it comes to tolerable clock skew. A way to obviate the global clock net is to partition the design into large synchronous blocks each having its own clock. Data with other blocks is exchanged asynchronously using handshake signals. Adopting such a strategy requires a methodology that supports: 1) a partitioning method dividing a design into the number of synchronous blocks such that the gain due to global clock net removal exceeds the communication overhead and 2) synthesis of handshake protocols to implement the data transfer between synchronous blocks. We describe this methodology and present results of applying it to a realistic design done in 0.25 micron, ranging in operating frequencies from 20 MHz to 1 GHz. The results show that the net power savings compared to fully synchronous designs are on an average about 30%},
  author       = {Meincke, Thomas and Hemani, Ahmed and Kumar, Shashi and Öberg, Johnny and Olsson, Thomas and Nilsson, Peter and Lindqvist, Dan and Tenhunen, Hannu},
  isbn         = {0-7803-5471-0},
  language     = {eng},
  pages        = {512--515},
  publisher    = {ARRAY(0xd01e358)},
  series       = {Proceedings of the 1999 IEEE International Symposium on Circuits and Systems, ISCAS '99.},
  title        = {Globally Asynchronous Locally Synchronous Architecture for Large High-performance ASICs},
  url          = {http://dx.doi.org/10.1109/ISCAS.1999.780794},
  volume       = {2},
  year         = {1999},
}