A methodology for arithmetic reduction of the static power consumption verified on filter architectures
(2008) The 20th International Conference on Microelectronics (ICM'08) In International Conference on Microelectronics ICM p.1114 Abstract (Swedish)
 Abstract in Undetermined
In today's technology generations, e.g. 90 and 65 nm, the static power consumption becomes a major contributor to the total power consumption. This paper focuses on the arithmetic level and shows a methodology for a substantial reduction of the static power consumption. Simulations are done in a typical 130 nm technology. Based on the simulation results, the static power in a digital filter is estimated and compared for two different architectures, one bitparallel respectively bitserial architecture. The paper shows a substantial reduction of the static power consumption when bitserial arithmetic is used. The paper also shows that the relative power reduction is strongly dependent on the used... (More)  Abstract in Undetermined
In today's technology generations, e.g. 90 and 65 nm, the static power consumption becomes a major contributor to the total power consumption. This paper focuses on the arithmetic level and shows a methodology for a substantial reduction of the static power consumption. Simulations are done in a typical 130 nm technology. Based on the simulation results, the static power in a digital filter is estimated and compared for two different architectures, one bitparallel respectively bitserial architecture. The paper shows a substantial reduction of the static power consumption when bitserial arithmetic is used. The paper also shows that the relative power reduction is strongly dependent on the used word length, i.e. the reduction is larger for longer word lengths. The reduction is dependent on the ratio between the arithmetic and the storage (the registers) as well. Architectures where the arithmetic dominates will show a larger reduction of the static power consumption. A static power reduction down to 37 % is shown for the bitserial filter architecture and a reduction down to 7 % is shown in the arithmetic in the filter. (Less)
Please use this url to cite or link to this publication:
http://lup.lub.lu.se/record/1241077
 author
 Nilsson, Peter ^{LU}
 organization
 publishing date
 2008
 type
 Chapter in Book/Report/Conference proceeding
 publication status
 published
 subject
 in
 International Conference on Microelectronics ICM
 pages
 4 pages
 publisher
 IEEEInstitute of Electrical and Electronics Engineers Inc.
 conference name
 The 20th International Conference on Microelectronics (ICM'08)
 external identifiers

 WOS:000279643200003
 Scopus:77951140252
 ISBN
 9781424423699
 DOI
 10.1109/ICM.2008.5393553
 language
 English
 LU publication?
 yes
 id
 0193ab6b44a44b8cb26d55e3e5e20ae2 (old id 1241077)
 date added to LUP
 20080919 14:54:00
 date last changed
 20161013 04:41:47
@misc{0193ab6b44a44b8cb26d55e3e5e20ae2, abstract = {<b>Abstract in Undetermined</b><br/><br> In today's technology generations, e.g. 90 and 65 nm, the static power consumption becomes a major contributor to the total power consumption. This paper focuses on the arithmetic level and shows a methodology for a substantial reduction of the static power consumption. Simulations are done in a typical 130 nm technology. Based on the simulation results, the static power in a digital filter is estimated and compared for two different architectures, one bitparallel respectively bitserial architecture. The paper shows a substantial reduction of the static power consumption when bitserial arithmetic is used. The paper also shows that the relative power reduction is strongly dependent on the used word length, i.e. the reduction is larger for longer word lengths. The reduction is dependent on the ratio between the arithmetic and the storage (the registers) as well. Architectures where the arithmetic dominates will show a larger reduction of the static power consumption. A static power reduction down to 37 % is shown for the bitserial filter architecture and a reduction down to 7 % is shown in the arithmetic in the filter.}, author = {Nilsson, Peter}, isbn = {9781424423699}, language = {eng}, pages = {1114}, publisher = {ARRAY(0x3bf4f70)}, series = {International Conference on Microelectronics ICM}, title = {A methodology for arithmetic reduction of the static power consumption verified on filter architectures}, url = {http://dx.doi.org/10.1109/ICM.2008.5393553}, year = {2008}, }