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Two 130nm CMOS class-D RF power amplifiers suitable for polar transmitter architectures

Cijvat, Pieternella LU and Sjöland, Henrik LU (2008) 9th International conference on solid-state and integrated circuit technology p.1372-1375
Abstract
Two class-D RF power amplifiers consisting of CMOS inverter chains have been designed and measured. The first amplifier operates at 1GHz and has a maximum output power of 12dBm, whereas the second operates at 1.5GHz and outputs a maximum of 6dBm. The amplifiers have been characterized for use in two different polar transmitter architectures, Pulse Width Modulation by Variable Gate Bias (PWMVGB) and Envelope Elimination and Restoration (EER). Using a standard 130nm digital CMOS process and off-chip passive components, maximum drain efficiencies of 32% and 39%, respectively, are achieved.

The two amplifiers are compared with respect to output power and drain efficiency, including a qualitative analysis of losses. Moreover, their use... (More)
Two class-D RF power amplifiers consisting of CMOS inverter chains have been designed and measured. The first amplifier operates at 1GHz and has a maximum output power of 12dBm, whereas the second operates at 1.5GHz and outputs a maximum of 6dBm. The amplifiers have been characterized for use in two different polar transmitter architectures, Pulse Width Modulation by Variable Gate Bias (PWMVGB) and Envelope Elimination and Restoration (EER). Using a standard 130nm digital CMOS process and off-chip passive components, maximum drain efficiencies of 32% and 39%, respectively, are achieved.

The two amplifiers are compared with respect to output power and drain efficiency, including a qualitative analysis of losses. Moreover, their use in the two polar transmitter architectures is discussed. (Less)
Please use this url to cite or link to this publication:
author
organization
publishing date
type
Contribution to conference
publication status
published
subject
keywords
polar transmitter, class D, CMOS, power amplifier
pages
4 pages
conference name
9th International conference on solid-state and integrated circuit technology
external identifiers
  • WOS:000265971002021
  • Scopus:60649096117
language
English
LU publication?
yes
id
e7f71805-9f00-4d84-a740-8c6cad37fbf2 (old id 1264741)
date added to LUP
2008-11-06 11:16:33
date last changed
2016-10-13 04:52:04
@misc{e7f71805-9f00-4d84-a740-8c6cad37fbf2,
  abstract     = {Two class-D RF power amplifiers consisting of CMOS inverter chains have been designed and measured. The first amplifier operates at 1GHz and has a maximum output power of 12dBm, whereas the second operates at 1.5GHz and outputs a maximum of 6dBm. The amplifiers have been characterized for use in two different polar transmitter architectures, Pulse Width Modulation by Variable Gate Bias (PWMVGB) and Envelope Elimination and Restoration (EER). Using a standard 130nm digital CMOS process and off-chip passive components, maximum drain efficiencies of 32% and 39%, respectively, are achieved.<br/><br>
The two amplifiers are compared with respect to output power and drain efficiency, including a qualitative analysis of losses. Moreover, their use in the two polar transmitter architectures is discussed.},
  author       = {Cijvat, Pieternella and Sjöland, Henrik},
  keyword      = {polar transmitter,class D,CMOS,power amplifier},
  language     = {eng},
  pages        = {1372--1375},
  title        = {Two 130nm CMOS class-D RF power amplifiers suitable for polar transmitter architectures},
  year         = {2008},
}