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Minimum-energy sub-threshold self-timed circuits: design methodology and a case study

Akgun, OmerCan LU ; Sparsø, Jens and Rodrigues, Joachim LU (2010) The 16th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC) In [Host publication title missing]
Abstract
This paper addresses the design of self-timed energy minimum circuits, operating in the sub-VT domain. The paper presents a generic implementation template using bundled-data circuitry and current sensing completion detection. To support this, a fully-decoupled latch controller has been developed, which integrates the current sensing circuitry. The paper outlines a corresponding design flow, which is based on contemporary synchronous EDA tools, and which transforms a synchronous design, into a corresponding self-timed circuit. The design flow and the current-sensing technique is validated by the implementation of an asynchronous version of a wavelet based event detector for cardiac pacemaker applications in a standard 65nm CMOS process.... (More)
This paper addresses the design of self-timed energy minimum circuits, operating in the sub-VT domain. The paper presents a generic implementation template using bundled-data circuitry and current sensing completion detection. To support this, a fully-decoupled latch controller has been developed, which integrates the current sensing circuitry. The paper outlines a corresponding design flow, which is based on contemporary synchronous EDA tools, and which transforms a synchronous design, into a corresponding self-timed circuit. The design flow and the current-sensing technique is validated by the implementation of an asynchronous version of a wavelet based event detector for cardiac pacemaker applications in a standard 65nm CMOS process. The chip has been fabricated and the area overhead due to power domain separation and completion detection circuitry

is 13.6 %. The improvement in throughput due to asynchronous operation is 52.58 %. By trading the throughput improvement, energy dissipation is reduced by 16.8% at the energy-minimum supply voltage. (Less)
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author
organization
publishing date
type
Chapter in Book/Report/Conference proceeding
publication status
in press
subject
in
[Host publication title missing]
pages
10 pages
publisher
IEEE--Institute of Electrical and Electronics Engineers Inc.
conference name
The 16th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC)
project
Digital ASIC: Implementation of Signal Processing Algorithms for Pacemakers
language
English
LU publication?
yes
id
984a2ae0-d36c-4fc1-8460-31efd403bd0a (old id 1544268)
date added to LUP
2010-02-11 12:45:59
date last changed
2016-04-16 09:07:07
@misc{984a2ae0-d36c-4fc1-8460-31efd403bd0a,
  abstract     = {This paper addresses the design of self-timed energy minimum circuits, operating in the sub-VT domain. The paper presents a generic implementation template using bundled-data circuitry and current sensing completion detection. To support this, a fully-decoupled latch controller has been developed, which integrates the current sensing circuitry. The paper outlines a corresponding design flow, which is based on contemporary synchronous EDA tools, and which transforms a synchronous design, into a corresponding self-timed circuit. The design flow and the current-sensing technique is validated by the implementation of an asynchronous version of a wavelet based event detector for cardiac pacemaker applications in a standard 65nm CMOS process. The chip has been fabricated and the area overhead due to power domain separation and completion detection circuitry<br/><br>
is 13.6 %. The improvement in throughput due to asynchronous operation is 52.58 %. By trading the throughput improvement, energy dissipation is reduced by 16.8% at the energy-minimum supply voltage.},
  author       = {Akgun, OmerCan and Sparsø, Jens and Rodrigues, Joachim},
  language     = {eng},
  pages        = {10},
  publisher    = {ARRAY(0xa008020)},
  series       = {[Host publication title missing]},
  title        = {Minimum-energy sub-threshold self-timed circuits: design methodology and a case study},
  year         = {2010},
}