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Reconfigurable cell array as enabler for supporting concurrent multiple standards in mobile terminals

Zhang, Chenxin LU ; Diaz, Isael LU ; Andersson, Per LU ; Rodrigues, Joachim LU and Öwall, Viktor LU (2010) Swedish System-on-Chip Conference 2010 (SSoCC'10)
Abstract
This manuscript presents an reconfigurable architecture, suitable to process time synchronization for multiple OFDM standards. The proposed architecture is based on a coarse-grained reconfigurable cell array, and the different radio standards under analysis are IEEE 802.11n, 3GPP Long Term Evolution and Digital Video Broadcast for cellular devices. With the use of a 2-by-2 cell array, composed of two decoupled processing and memory pairs, two concurrent data streams from any two of three radio standards are supported. Dynamic configuration of the cell array enables run-time switching between different standards, and the underlying hardware resources are shared when concurrent streams are processed. The enhanced RISC architecture of the... (More)
This manuscript presents an reconfigurable architecture, suitable to process time synchronization for multiple OFDM standards. The proposed architecture is based on a coarse-grained reconfigurable cell array, and the different radio standards under analysis are IEEE 802.11n, 3GPP Long Term Evolution and Digital Video Broadcast for cellular devices. With the use of a 2-by-2 cell array, composed of two decoupled processing and memory pairs, two concurrent data streams from any two of three radio standards are supported. Dynamic configuration of the cell array enables run-time switching between different standards, and the underlying hardware resources are shared when concurrent streams are processed. The enhanced RISC architecture of the processor cells contributes to a high instruction level parallelism, where the close interactions between processing and memory cells meet the stringent real-time processing requirement. The proposed 2-by-2 cell array is synthesized using a 65nm low-power regular threshold standard cell CMOS library, which occupies 0.338mm2 area and has a maximum clock frequency of 534MHz. The reconfigurable cell array offers a high flexibility while uses 1.83 times more area when compared to a function identical ASIC solution. (Less)
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author
; ; ; and
organization
publishing date
type
Chapter in Book/Report/Conference proceeding
publication status
published
subject
keywords
OFDM, Synchronization., Multi-standard, Reconfigurable cell array, CGRA
host publication
10th Swedish System-On-Chip Conference
pages
5 pages
publisher
Swedish Chapter of IEEE Solid-State Circuits Society (SSCS)
conference name
Swedish System-on-Chip Conference 2010 (SSoCC'10)
conference location
Kolmården, Sweden
conference dates
2010-05-03 - 2010-05-04
language
English
LU publication?
yes
id
7423fa91-d87f-4bf3-a0ca-3f01f53cbae9 (old id 1600011)
date added to LUP
2016-04-04 12:14:39
date last changed
2018-11-21 21:09:51
@inproceedings{7423fa91-d87f-4bf3-a0ca-3f01f53cbae9,
  abstract     = {{This manuscript presents an reconfigurable architecture, suitable to process time synchronization for multiple OFDM standards. The proposed architecture is based on a coarse-grained reconfigurable cell array, and the different radio standards under analysis are IEEE 802.11n, 3GPP Long Term Evolution and Digital Video Broadcast for cellular devices. With the use of a 2-by-2 cell array, composed of two decoupled processing and memory pairs, two concurrent data streams from any two of three radio standards are supported. Dynamic configuration of the cell array enables run-time switching between different standards, and the underlying hardware resources are shared when concurrent streams are processed. The enhanced RISC architecture of the processor cells contributes to a high instruction level parallelism, where the close interactions between processing and memory cells meet the stringent real-time processing requirement. The proposed 2-by-2 cell array is synthesized using a 65nm low-power regular threshold standard cell CMOS library, which occupies 0.338mm2 area and has a maximum clock frequency of 534MHz. The reconfigurable cell array offers a high flexibility while uses 1.83 times more area when compared to a function identical ASIC solution.}},
  author       = {{Zhang, Chenxin and Diaz, Isael and Andersson, Per and Rodrigues, Joachim and Öwall, Viktor}},
  booktitle    = {{10th Swedish System-On-Chip Conference}},
  keywords     = {{OFDM; Synchronization.; Multi-standard; Reconfigurable cell array; CGRA}},
  language     = {{eng}},
  publisher    = {{Swedish Chapter of IEEE Solid-State Circuits Society (SSCS)}},
  title        = {{Reconfigurable cell array as enabler for supporting concurrent multiple standards in mobile terminals}},
  year         = {{2010}},
}