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A low-jitter frequency synthesizer with dynamic phase interpolation for high-speed Ethernet

Lu, Ping LU ; Ye, Fan and Ren, Junyan (2006) IEEE International Symposium on Circuits and Systems, ISCAS 2006 In [Host publication title missing] p.2481-2484
Abstract
A frequency synthesizer applied to 1000Base-T Ethernet transceiver as well as 10/100Base-T mode is described. A dynamic voltage-mode phase interpolator is used and a more precise analysis and calculation on degressive interpolating resistors are given. The design not only meets the transmitter's requirement of very accurate rising (falling) edge control but also offers much finer time-interval clocks compared to VCO natural multi-phase outputs. The chip was implemented in SMIC 0.18-mum standard CMOS technology and achieves an RMS jitter of 11ps with the crystal oscillator reference RMS jitter of 16ps. The power is smaller than 4mW from a 1.8V power supply in all modes
Please use this url to cite or link to this publication:
author
publishing date
type
Chapter in Book/Report/Conference proceeding
publication status
published
subject
in
[Host publication title missing]
pages
2481 - 2484
conference name
IEEE International Symposium on Circuits and Systems, ISCAS 2006
external identifiers
  • Scopus:34547274155
ISBN
0-7803-9389-9
DOI
10.1109/ISCAS.2006.1693126
language
English
LU publication?
no
id
2e134f0d-d09a-4a06-a0ba-a3efbcea0cf1 (old id 1667540)
date added to LUP
2010-09-07 12:50:21
date last changed
2016-10-13 04:51:40
@misc{2e134f0d-d09a-4a06-a0ba-a3efbcea0cf1,
  abstract     = {A frequency synthesizer applied to 1000Base-T Ethernet transceiver as well as 10/100Base-T mode is described. A dynamic voltage-mode phase interpolator is used and a more precise analysis and calculation on degressive interpolating resistors are given. The design not only meets the transmitter's requirement of very accurate rising (falling) edge control but also offers much finer time-interval clocks compared to VCO natural multi-phase outputs. The chip was implemented in SMIC 0.18-mum standard CMOS technology and achieves an RMS jitter of 11ps with the crystal oscillator reference RMS jitter of 16ps. The power is smaller than 4mW from a 1.8V power supply in all modes},
  author       = {Lu, Ping and Ye, Fan and Ren, Junyan},
  isbn         = {0-7803-9389-9},
  language     = {eng},
  pages        = {2481--2484},
  series       = {[Host publication title missing]},
  title        = {A low-jitter frequency synthesizer with dynamic phase interpolation for high-speed Ethernet},
  url          = {http://dx.doi.org/10.1109/ISCAS.2006.1693126},
  year         = {2006},
}