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A 3.3v low-jitter frequency Synthesizer applied to fast Ethernet transceiver

Lu, Ping LU ; Wang, Yan; Li, Lian and Ren, Junyan (2005) In Journal of Semiconductors 26(8). p.1641-1645
Abstract
A frequency synthesizer applied to a 10/100Base-T ethernet transceiver is described. It can work adaptively in either a 10Mbps or 100Mbps mode and convert freely from on mode to another. Cascode current sources and differential delay cells are adopted to guarantee good performance. The circuit meets the requirements of both transmitter on rising/falling time and receiver on CDR so that additional power and area are saved. Under some testing circumstance, rms jitter is only 22ps (with reference jitter of 25ps). The testing results prove that the frequency synthesizer has good processing stability and rejection to various noise. It works well for both transmitters and receivers. The circuit is designed with SMIC 0.35um standard CMOS... (More)
A frequency synthesizer applied to a 10/100Base-T ethernet transceiver is described. It can work adaptively in either a 10Mbps or 100Mbps mode and convert freely from on mode to another. Cascode current sources and differential delay cells are adopted to guarantee good performance. The circuit meets the requirements of both transmitter on rising/falling time and receiver on CDR so that additional power and area are saved. Under some testing circumstance, rms jitter is only 22ps (with reference jitter of 25ps). The testing results prove that the frequency synthesizer has good processing stability and rejection to various noise. It works well for both transmitters and receivers. The circuit is designed with SMIC 0.35um standard CMOS technology and a power supply of 3.3v. (Less)
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author
publishing date
type
Contribution to journal
publication status
published
subject
keywords
Ethernet frequency synthesizer clock jitter
in
Journal of Semiconductors
volume
26
issue
8
pages
1641 - 1645
publisher
IOS Press
ISSN
1674-4926
language
Chinese
LU publication?
no
id
b39601e4-0e8a-46f2-b520-68a3c8d591af (old id 1667616)
alternative location
http://d.g.wanfangdata.com.cn/Periodical_bdtxb200508032.aspx
date added to LUP
2010-09-07 13:02:31
date last changed
2016-06-29 09:02:35
@misc{b39601e4-0e8a-46f2-b520-68a3c8d591af,
  abstract     = {A frequency synthesizer applied to a 10/100Base-T ethernet transceiver is described. It can work adaptively in either a 10Mbps or 100Mbps mode and convert freely from on mode to another. Cascode current sources and differential delay cells are adopted to guarantee good performance. The circuit meets the requirements of both transmitter on rising/falling time and receiver on CDR so that additional power and area are saved. Under some testing circumstance, rms jitter is only 22ps (with reference jitter of 25ps). The testing results prove that the frequency synthesizer has good processing stability and rejection to various noise. It works well for both transmitters and receivers. The circuit is designed with SMIC 0.35um standard CMOS technology and a power supply of 3.3v.},
  author       = {Lu, Ping and Wang, Yan and Li, Lian and Ren, Junyan},
  issn         = {1674-4926},
  keyword      = {Ethernet frequency synthesizer clock jitter},
  language     = {chi},
  number       = {8},
  pages        = {1641--1645},
  publisher    = {ARRAY(0xb15e9d8)},
  series       = {Journal of Semiconductors},
  title        = {A 3.3v low-jitter frequency Synthesizer applied to fast Ethernet transceiver},
  volume       = {26},
  year         = {2005},
}