Advanced

Energy efficiency in Sub-VT of various 16-bit adder structures in 65 nm CMOS

Sherazi, Syed Muhammad Yasser LU ; Rodrigues, Joachim LU and Nilsson, Peter LU (2010) Swedish System-on-Chip Conference 2010 (SSoCC'10)
Abstract
This manuscript presents simulation results of energy

dissipation in sub-threshold (sub-VT ) of various 16-bit

adder structures. The architectures designed for the comparative

experiments are, a bit-serial, an 8-bit digit-serial and a 16-bit

parallel adder structures. The designs are synthesized in a 65 nm

low-leakage high-threshold CMOS technology. The results show

that an energy minimum operating voltage exists for all the

three implementations, however the 8-bit digit serial has the least

energy minimum operating point. The advantage of the bit-serial

structure is that by employing this technique we may save 88%

area when compared to parallel... (More)
This manuscript presents simulation results of energy

dissipation in sub-threshold (sub-VT ) of various 16-bit

adder structures. The architectures designed for the comparative

experiments are, a bit-serial, an 8-bit digit-serial and a 16-bit

parallel adder structures. The designs are synthesized in a 65 nm

low-leakage high-threshold CMOS technology. The results show

that an energy minimum operating voltage exists for all the

three implementations, however the 8-bit digit serial has the least

energy minimum operating point. The advantage of the bit-serial

structure is that by employing this technique we may save 88%

area when compared to parallel implementation and 66% area

when compared to digital-serial implementation. (Less)
Please use this url to cite or link to this publication:
author
organization
publishing date
type
Contribution to conference
publication status
published
subject
keywords
Adder, sub-threshold, Energy Efficiency, sub-VT, 65 nm CMOS
conference name
Swedish System-on-Chip Conference 2010 (SSoCC'10)
language
English
LU publication?
yes
id
cfbddca9-9438-4902-b661-b2656b1591ba (old id 1667713)
date added to LUP
2011-01-11 11:45:08
date last changed
2016-07-14 15:39:03
@misc{cfbddca9-9438-4902-b661-b2656b1591ba,
  abstract     = {This manuscript presents simulation results of energy<br/><br>
dissipation in sub-threshold (sub-VT ) of various 16-bit<br/><br>
adder structures. The architectures designed for the comparative<br/><br>
experiments are, a bit-serial, an 8-bit digit-serial and a 16-bit<br/><br>
parallel adder structures. The designs are synthesized in a 65 nm<br/><br>
low-leakage high-threshold CMOS technology. The results show<br/><br>
that an energy minimum operating voltage exists for all the<br/><br>
three implementations, however the 8-bit digit serial has the least<br/><br>
energy minimum operating point. The advantage of the bit-serial<br/><br>
structure is that by employing this technique we may save 88%<br/><br>
area when compared to parallel implementation and 66% area<br/><br>
when compared to digital-serial implementation.},
  author       = {Sherazi, Syed Muhammad Yasser and Rodrigues, Joachim and Nilsson, Peter},
  keyword      = {Adder,sub-threshold,Energy Efficiency,sub-VT,65 nm CMOS},
  language     = {eng},
  title        = {Energy efficiency in Sub-VT of various 16-bit adder structures in 65 nm CMOS},
  year         = {2010},
}