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Low power analog channel decoder in sub-threshold 65nm CMOS

Meraji, Reza LU ; Anderson, John B LU and Öwall, Viktor LU (2010) Swedish System-on-Chip Conference 2010 (SSoCC'10) In [Host publication title missing]
Abstract
This paper presents the architecture and the corresponding

simulation results for a very low power half-rate

extended Hamming (8,4) decoder implemented in analog integrated

circuitry. TI’s 65nm low power CMOS design library

was used to simulate the complete decoder including an input

interface, an analog decoding core and an output interface. The

simulated bit error rate (BER) performance of the decoder is

presented and compared to the ideal performance expected from

the Hamming code. Transistor-level simulation results suggest

that a high throughput Hamming decoder up to 1 Mbits can be

implemented in analog circuits with a core power... (More)
This paper presents the architecture and the corresponding

simulation results for a very low power half-rate

extended Hamming (8,4) decoder implemented in analog integrated

circuitry. TI’s 65nm low power CMOS design library

was used to simulate the complete decoder including an input

interface, an analog decoding core and an output interface. The

simulated bit error rate (BER) performance of the decoder is

presented and compared to the ideal performance expected from

the Hamming code. Transistor-level simulation results suggest

that a high throughput Hamming decoder up to 1 Mbits can be

implemented in analog circuits with a core power consumption

as low as 6 μW. (Less)
Please use this url to cite or link to this publication:
author
organization
publishing date
type
Chapter in Book/Report/Conference proceeding
publication status
published
subject
keywords
sub-threshold CMOS, integrated circuits, low power circuits, Decoders
in
[Host publication title missing]
pages
4 pages
publisher
SSoCC conference
conference name
Swedish System-on-Chip Conference 2010 (SSoCC'10)
language
English
LU publication?
yes
id
67ad6381-dc7b-4797-a61a-ebc89889b342 (old id 1689598)
date added to LUP
2010-10-05 10:12:26
date last changed
2016-04-16 08:40:56
@misc{67ad6381-dc7b-4797-a61a-ebc89889b342,
  abstract     = {This paper presents the architecture and the corresponding<br/><br>
simulation results for a very low power half-rate<br/><br>
extended Hamming (8,4) decoder implemented in analog integrated<br/><br>
circuitry. TI’s 65nm low power CMOS design library<br/><br>
was used to simulate the complete decoder including an input<br/><br>
interface, an analog decoding core and an output interface. The<br/><br>
simulated bit error rate (BER) performance of the decoder is<br/><br>
presented and compared to the ideal performance expected from<br/><br>
the Hamming code. Transistor-level simulation results suggest<br/><br>
that a high throughput Hamming decoder up to 1 Mbits can be<br/><br>
implemented in analog circuits with a core power consumption<br/><br>
as low as 6 μW.},
  author       = {Meraji, Reza and Anderson, John B and Öwall, Viktor},
  keyword      = {sub-threshold CMOS,integrated circuits,low power circuits,Decoders},
  language     = {eng},
  pages        = {4},
  publisher    = {ARRAY(0xa2b86d8)},
  series       = {[Host publication title missing]},
  title        = {Low power analog channel decoder in sub-threshold 65nm CMOS},
  year         = {2010},
}