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High speed CMOS circuit technique

Yuan, Jiren LU and Svensson, Christer (1989) In IEEE Journal of Solid-State Circuits 24(1). p.62-70
Abstract
It is shown that clock frequencies in excess of 200 MHz are feasible in a 3-μm CMOS process. This performance can be obtained by means of clocking strategy, device sizing, and logic style selection. A precharge technique with a true single-phase clock, which increases the clock frequency and reduces the skew problems, is used. Device sizing with the help of an optimizing program improves circuit speed by a factor of 1.5-1.8. The logic depth is minimized to one instead of two or more, and pipeline structures are used wherever possible. Experimental results for several circuits which work at clock frequencies of 200-230 MHz are presented. SPICE simulation shows that some circuits could work up to 400-500 MHz
Please use this url to cite or link to this publication:
author
publishing date
type
Contribution to journal
publication status
published
subject
in
IEEE Journal of Solid-State Circuits
volume
24
issue
1
pages
62 - 70
publisher
IEEE--Institute of Electrical and Electronics Engineers Inc.
external identifiers
  • Scopus:0024611252
ISSN
0018-9200
DOI
10.1109/4.16303
language
English
LU publication?
no
id
d3918db4-c19f-44ed-9871-5b7b1b8cd4c3 (old id 1758994)
date added to LUP
2011-01-04 18:17:00
date last changed
2016-11-13 04:26:08
@misc{d3918db4-c19f-44ed-9871-5b7b1b8cd4c3,
  abstract     = {It is shown that clock frequencies in excess of 200 MHz are feasible in a 3-μm CMOS process. This performance can be obtained by means of clocking strategy, device sizing, and logic style selection. A precharge technique with a true single-phase clock, which increases the clock frequency and reduces the skew problems, is used. Device sizing with the help of an optimizing program improves circuit speed by a factor of 1.5-1.8. The logic depth is minimized to one instead of two or more, and pipeline structures are used wherever possible. Experimental results for several circuits which work at clock frequencies of 200-230 MHz are presented. SPICE simulation shows that some circuits could work up to 400-500 MHz},
  author       = {Yuan, Jiren and Svensson, Christer},
  issn         = {0018-9200},
  language     = {eng},
  number       = {1},
  pages        = {62--70},
  publisher    = {ARRAY(0xb9100b0)},
  series       = {IEEE Journal of Solid-State Circuits},
  title        = {High speed CMOS circuit technique},
  url          = {http://dx.doi.org/10.1109/4.16303},
  volume       = {24},
  year         = {1989},
}