Advanced

Efficient CMOS counter circuits

Yuan, Jiren LU (1988) In Electronics Letters 24(21). p.1311-1313
Abstract
Several efficient counters are presented. A nine-transistor divide-by-two circuit is used as a basic building block. With transistor sizing, an input frequency of 400 MHz can be adopted by an asynchronous counter, while an eight-bit synchronous counter can achieve clock rates of more than 200 MHz in a 3-μm CMOS process. The power consumption of the proposed precharged dynamic synchronous counter is reduced to almost half as much as normal
Please use this url to cite or link to this publication:
author
publishing date
type
Contribution to journal
publication status
published
subject
in
Electronics Letters
volume
24
issue
21
pages
1311 - 1313
publisher
IEE
external identifiers
  • Scopus:0024092714
ISSN
1350-911X
language
English
LU publication?
no
id
8c145720-8d65-4598-bee1-118a861b71ba (old id 1758998)
alternative location
http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=5891
date added to LUP
2011-01-04 18:25:57
date last changed
2016-10-13 04:29:29
@misc{8c145720-8d65-4598-bee1-118a861b71ba,
  abstract     = {Several efficient counters are presented. A nine-transistor divide-by-two circuit is used as a basic building block. With transistor sizing, an input frequency of 400 MHz can be adopted by an asynchronous counter, while an eight-bit synchronous counter can achieve clock rates of more than 200 MHz in a 3-μm CMOS process. The power consumption of the proposed precharged dynamic synchronous counter is reduced to almost half as much as normal},
  author       = {Yuan, Jiren},
  issn         = {1350-911X},
  language     = {eng},
  number       = {21},
  pages        = {1311--1313},
  publisher    = {ARRAY(0x86f1468)},
  series       = {Electronics Letters},
  title        = {Efficient CMOS counter circuits},
  volume       = {24},
  year         = {1988},
}