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3-D Integrated Track-and-Hold Circuit Using InAs Nanowire MOSFETs and Capacitors

Wu, Jun LU and Wernersson, Lars Erik LU (2016) In IEEE Electron Device Letters 37(7). p.851-854
Abstract

This letter presents a vertical integration scheme where track-and-hold circuits, consisting of a MOSFET in series with a metal-insulator-metal (MIM) capacitor, are successfully fabricated along vertical InAs nanowires. The nanowire MOSFET is used as a switch with varying switch resistance, Rsw, as the gate-source voltage, VGS, is varied. The track-and-hold circuit operation is verified by a sine wave that is properly evaluated by the circuit. In addition, calculations show that the three-dimensional integration reduces the track-and-hold area a factor of 2, as compared with planar MIM capacitor only. With further nanowire pitch reduction, about ten times area saving is projected.

Please use this url to cite or link to this publication:
author
organization
publishing date
type
Contribution to journal
publication status
published
subject
keywords
capacitor, InAs, mixed-signal application, MOSFET, Nanowire, track-and-hold circuit
in
IEEE Electron Device Letters
volume
37
issue
7
pages
4 pages
publisher
IEEE--Institute of Electrical and Electronics Engineers Inc.
external identifiers
  • Scopus:84976864087
ISSN
0741-3106
DOI
10.1109/LED.2016.2572188
language
English
LU publication?
yes
id
1bddf767-c0b2-4ec9-bb79-f4c5851ab682
date added to LUP
2016-07-18 12:27:12
date last changed
2016-07-18 12:27:12
@misc{1bddf767-c0b2-4ec9-bb79-f4c5851ab682,
  abstract     = {<p>This letter presents a vertical integration scheme where track-and-hold circuits, consisting of a MOSFET in series with a metal-insulator-metal (MIM) capacitor, are successfully fabricated along vertical InAs nanowires. The nanowire MOSFET is used as a switch with varying switch resistance, R<sub>sw</sub>, as the gate-source voltage, V<sub>GS</sub>, is varied. The track-and-hold circuit operation is verified by a sine wave that is properly evaluated by the circuit. In addition, calculations show that the three-dimensional integration reduces the track-and-hold area a factor of 2, as compared with planar MIM capacitor only. With further nanowire pitch reduction, about ten times area saving is projected.</p>},
  author       = {Wu, Jun and Wernersson, Lars Erik},
  issn         = {0741-3106},
  keyword      = {capacitor,InAs,mixed-signal application,MOSFET,Nanowire,track-and-hold circuit},
  language     = {eng},
  month        = {07},
  number       = {7},
  pages        = {851--854},
  publisher    = {ARRAY(0x85d8c80)},
  series       = {IEEE Electron Device Letters},
  title        = {3-D Integrated Track-and-Hold Circuit Using InAs Nanowire MOSFETs and Capacitors},
  url          = {http://dx.doi.org/10.1109/LED.2016.2572188},
  volume       = {37},
  year         = {2016},
}