Advanced

Test Scheduling for 3D Stacked ICs under Power Constraints

Sengupta, Breeta LU ; Ingelsson, Urban and Larsson, Erik LU (2011) 2nd IEEE International Workshop on Reliability Aware System Design and Test (RASDAT)
Abstract
This paper addresses Test Application Time (TAT) reduction for core-based 3D Stacked ICs (SICs). Applying traditional test scheduling methods used for non-stacked chip testing where the same test schedule is applied both at wafer test and at final test to SICs, leads to unnecessarily high TAT. This is because the final test of 3D-SICs includes the testing of all the stacked chips. A key challenge in 3D-SIC testing is to reduce TAT by co-optimizing the wafer test and the final test while meeting power constraints. We consider a system of chips with cores equipped with dedicated Built-In-Self-Test (BIST)-engines and propose a test scheduling approach to reduce TAT while meeting the power constraints. Depending on the test schedule, the... (More)
This paper addresses Test Application Time (TAT) reduction for core-based 3D Stacked ICs (SICs). Applying traditional test scheduling methods used for non-stacked chip testing where the same test schedule is applied both at wafer test and at final test to SICs, leads to unnecessarily high TAT. This is because the final test of 3D-SICs includes the testing of all the stacked chips. A key challenge in 3D-SIC testing is to reduce TAT by co-optimizing the wafer test and the final test while meeting power constraints. We consider a system of chips with cores equipped with dedicated Built-In-Self-Test (BIST)-engines and propose a test scheduling approach to reduce TAT while meeting the power constraints. Depending on the test schedule, the control lines that are required for BIST can be shared among several BIST engines. This is taken into account in the test scheduling approach and experiments show significant savings in TAT. (Less)
Please use this url to cite or link to this publication:
author
organization
publishing date
type
Contribution to conference
publication status
published
subject
keywords
Design for Test (DfT), Built in Self Test (BIST), Test scheduling, Sessions, Test time, Test cost, 3D Stacked Integrated Circuit (SIC), Through Silicon Via (TSV).
pages
6 pages
conference name
2nd IEEE International Workshop on Reliability Aware System Design and Test (RASDAT)
language
English
LU publication?
no
id
4f8e30a7-555f-4ab2-b49c-0e59bd64970f (old id 2340793)
date added to LUP
2012-02-10 13:45:00
date last changed
2016-04-16 12:27:15
@misc{4f8e30a7-555f-4ab2-b49c-0e59bd64970f,
  abstract     = {This paper addresses Test Application Time (TAT) reduction for core-based 3D Stacked ICs (SICs). Applying traditional test scheduling methods used for non-stacked chip testing where the same test schedule is applied both at wafer test and at final test to SICs, leads to unnecessarily high TAT. This is because the final test of 3D-SICs includes the testing of all the stacked chips. A key challenge in 3D-SIC testing is to reduce TAT by co-optimizing the wafer test and the final test while meeting power constraints. We consider a system of chips with cores equipped with dedicated Built-In-Self-Test (BIST)-engines and propose a test scheduling approach to reduce TAT while meeting the power constraints. Depending on the test schedule, the control lines that are required for BIST can be shared among several BIST engines. This is taken into account in the test scheduling approach and experiments show significant savings in TAT.},
  author       = {Sengupta, Breeta and Ingelsson, Urban and Larsson, Erik},
  keyword      = {Design for Test (DfT),Built in Self Test (BIST),Test scheduling,Sessions,Test time,Test cost,3D Stacked Integrated Circuit (SIC),Through Silicon Via (TSV).},
  language     = {eng},
  pages        = {6},
  title        = {Test Scheduling for 3D Stacked ICs under Power Constraints},
  year         = {2011},
}