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Core-Level Expansion of Compressed Test Patterns

Larsson, Anders; Zhang, Xin; Larsson, Erik LU and Chakrabarty, Krishnendu (2008) 17th Asian Test Symposium ATS In [Host publication title missing] p.277-277
Abstract
The increasing test-data volumes needed for the testing of system-on-chip (SOC) integrated circuits lead to long test-application times and high tester memory requirements. Efficient test planning and test-data compression are therefore needed. We present an analysis to highlight the fact that the impact of a test-data compression technique on test time and compression ratio are method-dependant as well as TAM-width dependant. This implies that for a given set of compression schemes, there is no compression scheme that is the optimal with respect to test time reduction and test-data compression at all TAM widths. We therefore propose a technique where we integrate core wrapper design, test architecture design and test scheduling with... (More)
The increasing test-data volumes needed for the testing of system-on-chip (SOC) integrated circuits lead to long test-application times and high tester memory requirements. Efficient test planning and test-data compression are therefore needed. We present an analysis to highlight the fact that the impact of a test-data compression technique on test time and compression ratio are method-dependant as well as TAM-width dependant. This implies that for a given set of compression schemes, there is no compression scheme that is the optimal with respect to test time reduction and test-data compression at all TAM widths. We therefore propose a technique where we integrate core wrapper design, test architecture design and test scheduling with test-data compression technique selection for each core in order to minimize the SOC test-application time and the test-data volume. Experimental results for several SOCs crafted from industrial cores demonstrate that the proposed method leads to significant reduction in test-data volume and test time. (Less)
Please use this url to cite or link to this publication:
author
publishing date
type
Chapter in Book/Report/Conference proceeding
publication status
published
subject
keywords
integrated circuits, system-on-chip, testing, test-data compression, memory requirements, wrapper design, test-application time
in
[Host publication title missing]
pages
277 - 277
publisher
IEEE--Institute of Electrical and Electronics Engineers Inc.
conference name
17th Asian Test Symposium ATS
external identifiers
  • Scopus:49749098371
language
English
LU publication?
no
id
be52888c-e4ee-4fc7-94e2-773e03b6943f (old id 2340963)
alternative location
http://www.ida.liu.se/labs/eslab/publications/pap/db/anlar_ats08.pdf
date added to LUP
2012-02-10 13:43:00
date last changed
2016-10-13 04:38:00
@misc{be52888c-e4ee-4fc7-94e2-773e03b6943f,
  abstract     = {The increasing test-data volumes needed for the testing of system-on-chip (SOC) integrated circuits lead to long test-application times and high tester memory requirements. Efficient test planning and test-data compression are therefore needed. We present an analysis to highlight the fact that the impact of a test-data compression technique on test time and compression ratio are method-dependant as well as TAM-width dependant. This implies that for a given set of compression schemes, there is no compression scheme that is the optimal with respect to test time reduction and test-data compression at all TAM widths. We therefore propose a technique where we integrate core wrapper design, test architecture design and test scheduling with test-data compression technique selection for each core in order to minimize the SOC test-application time and the test-data volume. Experimental results for several SOCs crafted from industrial cores demonstrate that the proposed method leads to significant reduction in test-data volume and test time.},
  author       = {Larsson, Anders and Zhang, Xin and Larsson, Erik and Chakrabarty, Krishnendu},
  keyword      = {integrated circuits,system-on-chip,testing,test-data compression,memory requirements,wrapper design,test-application time},
  language     = {eng},
  pages        = {277--277},
  publisher    = {ARRAY(0xa03d6a0)},
  series       = {[Host publication title missing]},
  title        = {Core-Level Expansion of Compressed Test Patterns},
  year         = {2008},
}