Advanced

System-on-Chip Test Bus Design and Test Scheduling

Larsson, Erik LU and Peng, Zebo (2000) International Test Synthesis Workshop,2000
Abstract
We propose a technique for test scheduling and test bus infrastructure design. In our approach, we consider constraints on the power consumption and on the design for test resources, while minimizing the test application time and the test bus length. The technique has a low computational cost which is important when it is used repeatedly in the design space exploration process. For the final design, we use Simulated annealing to optimize the solution. The proposed technique has been been implemented and experimental results show the efficiency of our approach.
Please use this url to cite or link to this publication:
author
publishing date
type
Contribution to conference
publication status
published
subject
keywords
testing, test scheduling, test bus infrastructure design, power consumption, simulated annealing
conference name
International Test Synthesis Workshop,2000
language
English
LU publication?
no
id
205bcfaf-472f-4350-b3b4-e79078c87006 (old id 2340971)
date added to LUP
2012-02-10 13:44:07
date last changed
2016-06-29 09:05:32
@misc{205bcfaf-472f-4350-b3b4-e79078c87006,
  abstract     = {We propose a technique for test scheduling and test bus infrastructure design. In our approach, we consider constraints on the power consumption and on the design for test resources, while minimizing the test application time and the test bus length. The technique has a low computational cost which is important when it is used repeatedly in the design space exploration process. For the final design, we use Simulated annealing to optimize the solution. The proposed technique has been been implemented and experimental results show the efficiency of our approach.},
  author       = {Larsson, Erik and Peng, Zebo},
  keyword      = {testing,test scheduling,test bus infrastructure design,power consumption,simulated annealing},
  language     = {eng},
  title        = {System-on-Chip Test Bus Design and Test Scheduling},
  year         = {2000},
}