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Optimization of a Bus-based Test Data Transportation Mechanism in System-on-Chip

Larsson, Anders; Larsson, Erik LU ; Eles, Petru Ion and Peng, Zebo (2005) 8th Euromicro Conference on Digital System Design DSD 2005 In [Host publication title missing] p.403-409
Abstract
The increasingamount of test data needed to test SOC (System-on-Chip) entailsefficient design of the TAM (test access mechanism), which is usedto transport test data inside the chip. Having a powerful TAM willshorten the test time, but it costs large silicon area to implementit. Hence, it is important to have an efficient TAM with minimalrequired hardware overhead. We propose a technique that makes useof the existing bus structure with additional buffers inserted ateach core to allow test application to the cores and test datatransportation over the bus to be performed asynchronously. Thenon-synchronization of test data transportation and testapplication makes it possible to perform concurrent testing ofcores while test data is transported... (More)
The increasingamount of test data needed to test SOC (System-on-Chip) entailsefficient design of the TAM (test access mechanism), which is usedto transport test data inside the chip. Having a powerful TAM willshorten the test time, but it costs large silicon area to implementit. Hence, it is important to have an efficient TAM with minimalrequired hardware overhead. We propose a technique that makes useof the existing bus structure with additional buffers inserted ateach core to allow test application to the cores and test datatransportation over the bus to be performed asynchronously. Thenon-synchronization of test data transportation and testapplication makes it possible to perform concurrent testing ofcores while test data is transported in a sequence. We haveimplemented a Tabu search based technique to optimize our testarchitecture, and the experimental results indicate that itproduces high quality results at low computationalcost. (Less)
Please use this url to cite or link to this publication:
author
publishing date
type
Chapter in Book/Report/Conference proceeding
publication status
published
subject
keywords
testing, system-on-chip, test access mechanism, TAM, bus structure, test data transportation
in
[Host publication title missing]
pages
403 - 409
publisher
IEEE--Institute of Electrical and Electronics Engineers Inc.
conference name
8th Euromicro Conference on Digital System Design DSD 2005
external identifiers
  • Scopus:33845303961
ISBN
0-7695-2433-8
DOI
10.1109/DSD.2005.59
language
English
LU publication?
no
id
5606d636-663a-4585-b6c1-8e960a22db61 (old id 2341072)
date added to LUP
2012-02-10 13:36:07
date last changed
2016-10-13 04:43:28
@misc{5606d636-663a-4585-b6c1-8e960a22db61,
  abstract     = {The increasingamount of test data needed to test SOC (System-on-Chip) entailsefficient design of the TAM (test access mechanism), which is usedto transport test data inside the chip. Having a powerful TAM willshorten the test time, but it costs large silicon area to implementit. Hence, it is important to have an efficient TAM with minimalrequired hardware overhead. We propose a technique that makes useof the existing bus structure with additional buffers inserted ateach core to allow test application to the cores and test datatransportation over the bus to be performed asynchronously. Thenon-synchronization of test data transportation and testapplication makes it possible to perform concurrent testing ofcores while test data is transported in a sequence. We haveimplemented a Tabu search based technique to optimize our testarchitecture, and the experimental results indicate that itproduces high quality results at low computationalcost.},
  author       = {Larsson, Anders and Larsson, Erik and Eles, Petru Ion and Peng, Zebo},
  isbn         = {0-7695-2433-8},
  keyword      = {testing,system-on-chip,test access mechanism,TAM,bus structure,test data transportation},
  language     = {eng},
  pages        = {403--409},
  publisher    = {ARRAY(0xc2b8ce8)},
  series       = {[Host publication title missing]},
  title        = {Optimization of a Bus-based Test Data Transportation Mechanism in System-on-Chip},
  url          = {http://dx.doi.org/10.1109/DSD.2005.59},
  year         = {2005},
}