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Test Planning for Core-based 3D Stacked ICs with Through-Silicon Vias

Sengupta, Breeta LU ; Ingelsson, Urban and Larsson, Erik LU (2012) 2012 25th International Conference on VLSI Design In [Host publication title missing] p.442-447
Abstract
Test planning for core-based 3D stacked ICs with trough-silicon vias (3D TSV-SIC) is different from test planning for non-stacked ICs as the same test schedule cannot be applied both at wafer sort and package test. In this paper, we assume a test flow where each chip is tested individually at wafer sort and jointly at package test. We define cost functions and test planning optimization algorithms for non-stacked ICs, 3D TSV-SICs with two chips and 3D TSV-SICs with an arbitrary number of chips. We have implemented our techniques and experiments show significant reduction of test cost.
Please use this url to cite or link to this publication:
author
organization
publishing date
type
Chapter in Book/Report/Conference proceeding
publication status
published
subject
keywords
Test Scheduling, 3D stacked IC, JTAG, Test Architecture, Through Silicon Via
in
[Host publication title missing]
pages
6 pages
publisher
IEEE--Institute of Electrical and Electronics Engineers Inc.
conference name
2012 25th International Conference on VLSI Design
external identifiers
  • Scopus:84859922138
DOI
10.1109/VLSID.2012.111
language
English
LU publication?
yes
id
64afbe24-af54-40d0-8cf6-98139ecf1a2e (old id 2733057)
date added to LUP
2012-06-07 15:06:03
date last changed
2016-10-13 04:45:11
@misc{64afbe24-af54-40d0-8cf6-98139ecf1a2e,
  abstract     = {Test planning for core-based 3D stacked ICs with trough-silicon vias (3D TSV-SIC) is different from test planning for non-stacked ICs as the same test schedule cannot be applied both at wafer sort and package test. In this paper, we assume a test flow where each chip is tested individually at wafer sort and jointly at package test. We define cost functions and test planning optimization algorithms for non-stacked ICs, 3D TSV-SICs with two chips and 3D TSV-SICs with an arbitrary number of chips. We have implemented our techniques and experiments show significant reduction of test cost.},
  author       = {Sengupta, Breeta and Ingelsson, Urban and Larsson, Erik},
  keyword      = {Test Scheduling,3D stacked IC,JTAG,Test Architecture,Through Silicon Via},
  language     = {eng},
  pages        = {442--447},
  publisher    = {ARRAY(0x9ed2cc8)},
  series       = {[Host publication title missing]},
  title        = {Test Planning for Core-based 3D Stacked ICs with Through-Silicon Vias},
  url          = {http://dx.doi.org/10.1109/VLSID.2012.111},
  year         = {2012},
}