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On Hardware Implementation of Radix 3 and Radix 5 FFT Kernels for LTE systems

Löfgren, Johan LU and Nilsson, Peter LU (2011) 29th Norchip conference, 2011 In [Host publication title missing]
Abstract (Swedish)
Abstract in Undetermined

This paper treats the hardware architecture and

implementation of mixed radix FFTs with cores of radix 3 and

radix 5 in addition to the standard radix 2 core. The implementation

flow graphs of the higher radix cores are presented

together with a description of how these cores afTect a pipelined

FFT implementation. It is shown that the mixed radix FFT is

more expensive than the radix 2 implementation - a mixed radix

FFT of 1200 points require 36 real multipliers in a pipelined

implementation whereas a 2048 radix 2 FFT needs 30 real

multipliers. However, half of the multipliers in the mixed radix

case can be... (More)
Abstract in Undetermined

This paper treats the hardware architecture and

implementation of mixed radix FFTs with cores of radix 3 and

radix 5 in addition to the standard radix 2 core. The implementation

flow graphs of the higher radix cores are presented

together with a description of how these cores afTect a pipelined

FFT implementation. It is shown that the mixed radix FFT is

more expensive than the radix 2 implementation - a mixed radix

FFT of 1200 points require 36 real multipliers in a pipelined

implementation whereas a 2048 radix 2 FFT needs 30 real

multipliers. However, half of the multipliers in the mixed radix

case can be constant. Therefore it is still feasible to use the mixed

radix FFT if an algorithm calls for it. (Less)
Please use this url to cite or link to this publication:
author
organization
publishing date
type
Chapter in Book/Report/Conference proceeding
publication status
published
subject
in
[Host publication title missing]
conference name
29th Norchip conference, 2011
external identifiers
  • Scopus:84856914450
ISBN
978-1-4577-0514-4
DOI
10.1109/NORCHP.2011.6126703
language
English
LU publication?
yes
id
0d367803-510a-4e5d-beda-b028c1fbe409 (old id 2856180)
date added to LUP
2012-07-03 14:38:45
date last changed
2016-10-13 04:56:18
@misc{0d367803-510a-4e5d-beda-b028c1fbe409,
  abstract     = {<b>Abstract in Undetermined</b><br/><br>
This paper treats the hardware architecture and<br/><br>
implementation of mixed radix FFTs with cores of radix 3 and<br/><br>
radix 5 in addition to the standard radix 2 core. The implementation<br/><br>
flow graphs of the higher radix cores are presented<br/><br>
together with a description of how these cores afTect a pipelined<br/><br>
FFT implementation. It is shown that the mixed radix FFT is<br/><br>
more expensive than the radix 2 implementation - a mixed radix<br/><br>
FFT of 1200 points require 36 real multipliers in a pipelined<br/><br>
implementation whereas a 2048 radix 2 FFT needs 30 real<br/><br>
multipliers. However, half of the multipliers in the mixed radix<br/><br>
case can be constant. Therefore it is still feasible to use the mixed<br/><br>
radix FFT if an algorithm calls for it.},
  author       = {Löfgren, Johan and Nilsson, Peter},
  isbn         = {978-1-4577-0514-4},
  language     = {eng},
  series       = {[Host publication title missing]},
  title        = {On Hardware Implementation of Radix 3 and Radix 5 FFT Kernels for LTE systems},
  url          = {http://dx.doi.org/10.1109/NORCHP.2011.6126703},
  year         = {2011},
}