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Digital background calibration in continuous-time delta-sigma analog to digital converters

Tan, Siyu LU ; Miao, Yun; Andersson, Mattias LU ; Rodrigues, Joachim LU and Andreani, Piero LU (2015) Nordic Circuits and Systems Conference (NORCAS): NORCHIP & International Symposium on System-on-Chip (SoC) In Nordic Circuits and Systems Conference (NORCAS): NORCHIP & International Symposium on System-on-Chip (SoC), 2015
Abstract
This work presents a digital calibration technique in continuous-time (CT) ΔΣ analog to digital (A/D) converters. The converter is clocked at 144MHz with a low oversampling ratio (OSR) of only 8. Dynamic element matching (DEM) is not efficient to linearize the digital to analog converter (DAC) when the OSR is very low. Therefore, non-idealities in the outermost multi-bit feedback DAC are measured and then removed in the background by a digital circuit. A third-order, four-bit feedback, single-loop CT ΔΣ converter with digital background calibration circuit has been designed, simulated and implemented in 65nm CMOS process. The maximum simulated signal-to-noise and distortion ratio (SNDR) is 67.1dB within 9MHz bandwidth.
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author
organization
publishing date
type
Chapter in Book/Report/Conference proceeding
publication status
published
subject
keywords
Delta-Sigma, Digital calibration
in
Nordic Circuits and Systems Conference (NORCAS): NORCHIP & International Symposium on System-on-Chip (SoC), 2015
publisher
IEEE--Institute of Electrical and Electronics Engineers Inc.
conference name
Nordic Circuits and Systems Conference (NORCAS): NORCHIP & International Symposium on System-on-Chip (SoC)
external identifiers
  • Scopus:84963727277
DOI
10.1109/NORCHIP.2015.7364377
language
English
LU publication?
yes
id
353b8561-8bd4-44a3-89e9-a1801f6cdf3d
date added to LUP
2016-06-07 15:56:30
date last changed
2016-10-13 05:09:53
@misc{353b8561-8bd4-44a3-89e9-a1801f6cdf3d,
  abstract     = {This work presents a digital calibration technique in continuous-time (CT) ΔΣ analog to digital (A/D) converters. The converter is clocked at 144MHz with a low oversampling ratio (OSR) of only 8. Dynamic element matching (DEM) is not efficient to linearize the digital to analog converter (DAC) when the OSR is very low. Therefore, non-idealities in the outermost multi-bit feedback DAC are measured and then removed in the background by a digital circuit. A third-order, four-bit feedback, single-loop CT ΔΣ converter with digital background calibration circuit has been designed, simulated and implemented in 65nm CMOS process. The maximum simulated signal-to-noise and distortion ratio (SNDR) is 67.1dB within 9MHz bandwidth.},
  author       = {Tan, Siyu and Miao, Yun and Andersson, Mattias and Rodrigues, Joachim and Andreani, Piero},
  keyword      = {Delta-Sigma,Digital calibration},
  language     = {eng},
  publisher    = {ARRAY(0xbd1b548)},
  series       = {Nordic Circuits and Systems Conference (NORCAS): NORCHIP & International Symposium on System-on-Chip (SoC), 2015 },
  title        = {Digital background calibration in continuous-time delta-sigma analog to digital converters},
  url          = {http://dx.doi.org/10.1109/NORCHIP.2015.7364377 },
  year         = {2015},
}