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Test Cost Modeling for 3D Stacked Chips with Through-Silicon Vias

Sengupta, Breeta LU ; Ingelsson, Urban and Larsson, Erik LU (2011) Swedish System-on-Chip Conference, SSoCC 2011
Abstract
In this paper we have proposed a test cost model for

core-based 3D Stacked ICs (SICs) connected by Through Silicon

Vias (TSVs). Unlike in the case of non-stacked chips, where the

test flow is well defined by applying the same test schedule both

at wafer sort and at package test, the most cost-efficient test

flow for 3D TSV-SICs is yet undefined. Therefore, analysing the

various alternatives of test flow, we present a cost model with

the optimal test flow. In the test flow alternatives, we analyse the

effect of all possible moments of testing for a 3D TSV-SIC, viz.,

wafer sort, intermediate test and package test. For the optimal

test flow, we have... (More)
In this paper we have proposed a test cost model for

core-based 3D Stacked ICs (SICs) connected by Through Silicon

Vias (TSVs). Unlike in the case of non-stacked chips, where the

test flow is well defined by applying the same test schedule both

at wafer sort and at package test, the most cost-efficient test

flow for 3D TSV-SICs is yet undefined. Therefore, analysing the

various alternatives of test flow, we present a cost model with

the optimal test flow. In the test flow alternatives, we analyse the

effect of all possible moments of testing for a 3D TSV-SIC, viz.,

wafer sort, intermediate test and package test. For the optimal

test flow, we have performed experiments with various varying

yield and test time parameters, which further support our claim. (Less)
Please use this url to cite or link to this publication:
author
organization
publishing date
type
Contribution to conference
publication status
published
subject
keywords
DfT (Design for test), Test Architecture, Scan chain, Wrapper Chain, Test Scheduling, Test Time., 3D Stacked Integrated Circuit (SIC)
pages
4 pages
conference name
Swedish System-on-Chip Conference, SSoCC 2011
language
English
LU publication?
no
id
6be3469a-f7ac-48b0-a588-9786ee5dda76 (old id 4302358)
date added to LUP
2014-02-13 10:40:20
date last changed
2016-07-14 15:39:33
@misc{6be3469a-f7ac-48b0-a588-9786ee5dda76,
  abstract     = {In this paper we have proposed a test cost model for<br/><br>
core-based 3D Stacked ICs (SICs) connected by Through Silicon<br/><br>
Vias (TSVs). Unlike in the case of non-stacked chips, where the<br/><br>
test flow is well defined by applying the same test schedule both<br/><br>
at wafer sort and at package test, the most cost-efficient test<br/><br>
flow for 3D TSV-SICs is yet undefined. Therefore, analysing the<br/><br>
various alternatives of test flow, we present a cost model with<br/><br>
the optimal test flow. In the test flow alternatives, we analyse the<br/><br>
effect of all possible moments of testing for a 3D TSV-SIC, viz.,<br/><br>
wafer sort, intermediate test and package test. For the optimal<br/><br>
test flow, we have performed experiments with various varying<br/><br>
yield and test time parameters, which further support our claim.},
  author       = {Sengupta, Breeta and Ingelsson, Urban and Larsson, Erik},
  keyword      = {DfT (Design for test),Test Architecture,Scan chain,Wrapper Chain,Test Scheduling,Test Time.,3D Stacked Integrated Circuit (SIC)},
  language     = {eng},
  pages        = {4},
  title        = {Test Cost Modeling for 3D Stacked Chips with Through-Silicon Vias},
  year         = {2011},
}