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Dynamically Reconfigurable Architectures for Real-time Baseband Processing

Zhang, Chenxin LU (2014)
Abstract
Motivated by challenges from today's fast-evolving wireless communication standards and soaring silicon design cost, it is important to design a flexible hardware platform that can be dynamically reconfigured to adapt to current operating scenarios, provide seamless handover between different communication networks, and extend the longevity of advanced systems. Moreover, increasingly sophisticated baseband processing algorithms pose stringent requirements of real-time processing for hardware implementations, especially for power-budget limited mobile terminals. With existing hardware platforms such as Application-Specific Integrated Circuits (ASICs), Field-Programmable Gate Arrays (FPGAs), and Digital Signal Processors (DSPs), the... (More)
Motivated by challenges from today's fast-evolving wireless communication standards and soaring silicon design cost, it is important to design a flexible hardware platform that can be dynamically reconfigured to adapt to current operating scenarios, provide seamless handover between different communication networks, and extend the longevity of advanced systems. Moreover, increasingly sophisticated baseband processing algorithms pose stringent requirements of real-time processing for hardware implementations, especially for power-budget limited mobile terminals. With existing hardware platforms such as Application-Specific Integrated Circuits (ASICs), Field-Programmable Gate Arrays (FPGAs), and Digital Signal Processors (DSPs), the contradictory design requirements of flexibility, computational performance, and hardware efficiency cannot be attained at the same time.



To achieve a balance between the aforementioned design requirements, a coarse-grained dynamically reconfigurable cell array architecture is proposed. The architecture is constructed from an array of heterogeneous function units interconnected through a hierarchical on-chip network. The adopted in-cell configuration scheme enables fast context switching between standards and between computational tasks during run-time. Although cell array is a generic hardware platform, this thesis focuses on the architectural development of the cell array tailored specifically for digital baseband processing of contemporary wireless communication systems. Various degrees of flexibilities among operating scenarios, algorithms, tasks, and supporting standards are exploited. Besides, high hardware efficiency is attained by conducting algorithm-architecture, hardware-software, and processing-memory co-design.



In this thesis, flexibility, performance and efficiency of the proposed architecture are demonstrated through two case studies. First, the cell array is deployed in a digital front-end receiver, aiming to support concurrent processing of multiple radio standards, 3GPP Long Term Evolution (LTE), IEEE 802.11n, and Digital Video Broadcasting for Handheld (DVB-H). Dynamic configuration of the cell array enables run-time switching between different operation modes, multi-standard single-stream and multi-standard multi-stream, in order to maximize hardware usage for attaining high computational performance while sufficing current processing demands. Implementation results show that the immense flexibility offered by the cell array comes at the cost of only about 16% area overhead in comparison to its ASIC counterpart. In the second study, the cell array architecture is extended with extensive vector computing capabilities, aiming to perform high-throughput MIMO signal processing. As an illustration, three computationally intensive blocks, namely channel estimation, pre-processing, and symbol detection, of a 4x4 MIMO processing chain in a 20 MHz 64-QAM 3GPP LTE-Advanced downlink are mapped and processed in real-time. With 6 processing and 10 memory cells deployed in the array, the achieved system throughput is 368 Mb/s at 500 MHz and the corresponding energy consumption for processing one information bit is 1.49 nJ/b. Compared to state-of-the-art implementations, the proposed solution outperforms related programmable platforms by up to 6 orders of magnitude in energy efficiency, and is 1.7-13.6 and 1.4-15 times less efficient than ASICs in terms of area and energy, respectively, when performing each individual task. (Less)
Please use this url to cite or link to this publication:
author
supervisor
opponent
  • Professor De Sutter, Bjorn, Ghent University, Belgium
organization
publishing date
type
Thesis
publication status
published
subject
keywords
Reconfigurable Computing, Coarse-Grained Architecture, Dynamic Reconfiguration, SIMD, VLIW, ASIP, Vector Processor, Baseband Processing, OFDM, MIMO, Channel Estimation, Symbol Detection.
pages
200 pages
defense location
Lecture hall E:1406, Department of Electrical and Information Technology, Ole Römers väg 3, Lund University Faculty of Engineering
defense date
2014-05-27 10:15
ISBN
978-91-7473-974-9
project
HiPEC
EIT_SOS VINNOVA Industrial Excellence Center - System Design on Silicon
language
English
LU publication?
yes
id
42c0682d-d9dd-4de9-9efc-5954adf0a74b (old id 4406448)
date added to LUP
2014-05-12 12:36:39
date last changed
2016-09-19 08:45:18
@misc{42c0682d-d9dd-4de9-9efc-5954adf0a74b,
  abstract     = {Motivated by challenges from today's fast-evolving wireless communication standards and soaring silicon design cost, it is important to design a flexible hardware platform that can be dynamically reconfigured to adapt to current operating scenarios, provide seamless handover between different communication networks, and extend the longevity of advanced systems. Moreover, increasingly sophisticated baseband processing algorithms pose stringent requirements of real-time processing for hardware implementations, especially for power-budget limited mobile terminals. With existing hardware platforms such as Application-Specific Integrated Circuits (ASICs), Field-Programmable Gate Arrays (FPGAs), and Digital Signal Processors (DSPs), the contradictory design requirements of flexibility, computational performance, and hardware efficiency cannot be attained at the same time.<br/><br>
<br/><br>
To achieve a balance between the aforementioned design requirements, a coarse-grained dynamically reconfigurable cell array architecture is proposed. The architecture is constructed from an array of heterogeneous function units interconnected through a hierarchical on-chip network. The adopted in-cell configuration scheme enables fast context switching between standards and between computational tasks during run-time. Although cell array is a generic hardware platform, this thesis focuses on the architectural development of the cell array tailored specifically for digital baseband processing of contemporary wireless communication systems. Various degrees of flexibilities among operating scenarios, algorithms, tasks, and supporting standards are exploited. Besides, high hardware efficiency is attained by conducting algorithm-architecture, hardware-software, and processing-memory co-design.<br/><br>
<br/><br>
In this thesis, flexibility, performance and efficiency of the proposed architecture are demonstrated through two case studies. First, the cell array is deployed in a digital front-end receiver, aiming to support concurrent processing of multiple radio standards, 3GPP Long Term Evolution (LTE), IEEE 802.11n, and Digital Video Broadcasting for Handheld (DVB-H). Dynamic configuration of the cell array enables run-time switching between different operation modes, multi-standard single-stream and multi-standard multi-stream, in order to maximize hardware usage for attaining high computational performance while sufficing current processing demands. Implementation results show that the immense flexibility offered by the cell array comes at the cost of only about 16% area overhead in comparison to its ASIC counterpart. In the second study, the cell array architecture is extended with extensive vector computing capabilities, aiming to perform high-throughput MIMO signal processing. As an illustration, three computationally intensive blocks, namely channel estimation, pre-processing, and symbol detection, of a 4x4 MIMO processing chain in a 20 MHz 64-QAM 3GPP LTE-Advanced downlink are mapped and processed in real-time. With 6 processing and 10 memory cells deployed in the array, the achieved system throughput is 368 Mb/s at 500 MHz and the corresponding energy consumption for processing one information bit is 1.49 nJ/b. Compared to state-of-the-art implementations, the proposed solution outperforms related programmable platforms by up to 6 orders of magnitude in energy efficiency, and is 1.7-13.6 and 1.4-15 times less efficient than ASICs in terms of area and energy, respectively, when performing each individual task.},
  author       = {Zhang, Chenxin},
  isbn         = {978-91-7473-974-9},
  keyword      = {Reconfigurable Computing,Coarse-Grained Architecture,Dynamic Reconfiguration,SIMD,VLIW,ASIP,Vector Processor,Baseband Processing,OFDM,MIMO,Channel Estimation,Symbol Detection.},
  language     = {eng},
  pages        = {200},
  title        = {Dynamically Reconfigurable Architectures for Real-time Baseband Processing},
  year         = {2014},
}