Test Planning and Test Access Mechanism Design for 3D SICs
Sengupta, Breeta LU and Larsson, Erik LU
(2014)
Swedish System on Chip Conference (SSoCC), 2014
- Abstract
- In this paper we propose a scheme for test planning
and test access mechanism (TAM) design for stacked integrated
circuits (SICs) that are designed in a core-based manner. Our
scheme minimizes the test cost, which is given as the weighted
sum of the test time and the TAM width. The test cost is evaluated
for a test flow that consists of a wafer sort test of each individual
chip and a package test of the complete stack of chips. We
use an Integer Linear Programming (ILP) model to find the optimal
test cost. The ILP model is implemented on several designs
constructed from ITC’02 benchmarks. The experimental results
show significant reduction in test... (More) - In this paper we propose a scheme for test planning
and test access mechanism (TAM) design for stacked integrated
circuits (SICs) that are designed in a core-based manner. Our
scheme minimizes the test cost, which is given as the weighted
sum of the test time and the TAM width. The test cost is evaluated
for a test flow that consists of a wafer sort test of each individual
chip and a package test of the complete stack of chips. We
use an Integer Linear Programming (ILP) model to find the optimal
test cost. The ILP model is implemented on several designs
constructed from ITC’02 benchmarks. The experimental results
show significant reduction in test cost compared to when using
schemes, which are optimized for non-stacked chips. (Less)
Please use this url to cite or link to this publication:
https://lup.lub.lu.se/record/4645552
- author
- Sengupta, Breeta
LU
and Larsson, Erik
LU
- organization
- publishing date
- 2014
- type
- Chapter in Book/Report/Conference proceeding
- publication status
- published
- subject
- keywords
- Design for Test (DfT), Test architecture, IEEE 1500, Test scheduling, Sessions, Test time, Test cost, 3D Stacked Integrated Circuit (SIC), Through Silicon Via (TSV).
- host publication
- [Host publication title missing]
- pages
- 6 pages
- publisher
- Swedish System on Chip Conference (SSoCC)
- conference name
- Swedish System on Chip Conference (SSoCC), 2014
- conference location
- Vadstena, Sweden
- conference dates
- 2014-05-12 - 2014-05-13
- language
- English
- LU publication?
- yes
- id
- 224dff65-454e-4d4d-af14-e5e5913ff0d4 (old id 4645552)
- date added to LUP
- 2016-04-04 11:23:56
- date last changed
- 2018-11-21 21:04:35
@inproceedings{224dff65-454e-4d4d-af14-e5e5913ff0d4,
abstract = {{In this paper we propose a scheme for test planning<br/><br>
and test access mechanism (TAM) design for stacked integrated<br/><br>
circuits (SICs) that are designed in a core-based manner. Our<br/><br>
scheme minimizes the test cost, which is given as the weighted<br/><br>
sum of the test time and the TAM width. The test cost is evaluated<br/><br>
for a test flow that consists of a wafer sort test of each individual<br/><br>
chip and a package test of the complete stack of chips. We<br/><br>
use an Integer Linear Programming (ILP) model to find the optimal<br/><br>
test cost. The ILP model is implemented on several designs<br/><br>
constructed from ITC’02 benchmarks. The experimental results<br/><br>
show significant reduction in test cost compared to when using<br/><br>
schemes, which are optimized for non-stacked chips.}},
author = {{Sengupta, Breeta and Larsson, Erik}},
booktitle = {{[Host publication title missing]}},
keywords = {{Design for Test (DfT); Test architecture; IEEE 1500; Test scheduling; Sessions; Test time; Test cost; 3D Stacked Integrated Circuit (SIC); Through Silicon Via (TSV).}},
language = {{eng}},
publisher = {{Swedish System on Chip Conference (SSoCC)}},
title = {{Test Planning and Test Access Mechanism Design for 3D SICs}},
url = {{https://lup.lub.lu.se/search/files/5764536/4645554.pdf}},
year = {{2014}},
}