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Custom Silicon Implementation of a Delayless Acoustic Echo Canceller Algorithm

Berkeman, Anders LU and Öwall, Viktor LU (2003) ESSCIRC, 2003 In [Host publication title missing] p.205-208
Abstract
This paper presents a hardware implementation of a

high quality acoustic echo canceller for use in handsfree

telecommunication systems. The implementation

is based on an algorithm with no delay in the signal

path, attractive for communication systems where low

delay is crucial. However, a zero delay algorithm has

higher complexity compared to other canceller solutions.

A custom silicon implementation fulfills quality

and realtime operation while sustaining a low power

consumption. The fabricated processor contains two

million transistors, and the core occupies 20 mm2 in a

0.35 pm CMOS process. At 16 MHz clock frequency,

the chip... (More)
This paper presents a hardware implementation of a

high quality acoustic echo canceller for use in handsfree

telecommunication systems. The implementation

is based on an algorithm with no delay in the signal

path, attractive for communication systems where low

delay is crucial. However, a zero delay algorithm has

higher complexity compared to other canceller solutions.

A custom silicon implementation fulfills quality

and realtime operation while sustaining a low power

consumption. The fabricated processor contains two

million transistors, and the core occupies 20 mm2 in a

0.35 pm CMOS process. At 16 MHz clock frequency,

the chip processes 16 bit samples at a rate of 16 kHz,

while consuming 55 mW for uncorrelated input data. (Less)
Please use this url to cite or link to this publication:
author
publishing date
type
Chapter in Book/Report/Conference proceeding
publication status
published
subject
in
[Host publication title missing]
pages
4 pages
conference name
ESSCIRC, 2003
external identifiers
  • Scopus:14544267403
ISBN
0-7803-7995-0
DOI
10.1109/ESSCIRC.2003.1257108
language
English
LU publication?
no
id
d8ab076e-87b0-4bfe-8562-78a0a1c881fd (old id 602770)
date added to LUP
2007-11-19 14:39:28
date last changed
2016-10-13 04:56:13
@misc{d8ab076e-87b0-4bfe-8562-78a0a1c881fd,
  abstract     = {This paper presents a hardware implementation of a<br/><br>
high quality acoustic echo canceller for use in handsfree<br/><br>
telecommunication systems. The implementation<br/><br>
is based on an algorithm with no delay in the signal<br/><br>
path, attractive for communication systems where low<br/><br>
delay is crucial. However, a zero delay algorithm has<br/><br>
higher complexity compared to other canceller solutions.<br/><br>
A custom silicon implementation fulfills quality<br/><br>
and realtime operation while sustaining a low power<br/><br>
consumption. The fabricated processor contains two<br/><br>
million transistors, and the core occupies 20 mm2 in a<br/><br>
0.35 pm CMOS process. At 16 MHz clock frequency,<br/><br>
the chip processes 16 bit samples at a rate of 16 kHz,<br/><br>
while consuming 55 mW for uncorrelated input data.},
  author       = {Berkeman, Anders and Öwall, Viktor},
  isbn         = {0-7803-7995-0},
  language     = {eng},
  pages        = {205--208},
  series       = {[Host publication title missing]},
  title        = {Custom Silicon Implementation of a Delayless Acoustic Echo Canceller Algorithm},
  url          = {http://dx.doi.org/10.1109/ESSCIRC.2003.1257108},
  year         = {2003},
}