Advanced

Circuits and devices with integrated VFETs and RTDs

Wernersson, Lars-Erik LU ; Lind, Erik LU ; Lindström, Peter LU and Andreani, Pietro LU (2002) In 2002 IEEE International Symposium on Circuits and Systems. Proceedings (Cat. No.02CH37353) p.205-208
Abstract
We have realised a new technology for the integration of VFETs and RTDs. For these tunnelling transistors (so called resonant tunnelling permeable base transistors) we have developed large signal models which have been implemented in a Cadence simulation environment. The DC I-V characteristics are reproduced to a very high degree in these models. The models are further used for simulations of the behaviour of simple small-scale circuits including resonant tunnelling transistors. Examples of circuits studied are a monostable-bistable logic element and a ternary quantiser, where the later is based on a new 3D architecture of RTDs and VFETs
Please use this url to cite or link to this publication:
author
organization
publishing date
type
Chapter in Book/Report/Conference proceeding
publication status
published
subject
keywords
VFETs, large signal models, Cadence simulation environment, DC I-V characteristics, monostable-bistable logic element, small-scale circuits, 3D architecture, ternary quantiser, RTDs, resonant tunnelling permeable base transistors
in
2002 IEEE International Symposium on Circuits and Systems. Proceedings (Cat. No.02CH37353)
pages
205 - 208
publisher
IEEE--Institute of Electrical and Electronics Engineers Inc.
external identifiers
  • WOS:000186328700052
  • Scopus:0036297317
ISBN
0-7803-7448-7
DOI
10.1109/ISCAS.2002.1010676
language
English
LU publication?
yes
id
7198542f-0c5a-4475-be34-0a13aed9dc15 (old id 611251)
date added to LUP
2007-11-29 12:11:45
date last changed
2016-10-13 04:43:56
@misc{7198542f-0c5a-4475-be34-0a13aed9dc15,
  abstract     = {We have realised a new technology for the integration of VFETs and RTDs. For these tunnelling transistors (so called resonant tunnelling permeable base transistors) we have developed large signal models which have been implemented in a Cadence simulation environment. The DC I-V characteristics are reproduced to a very high degree in these models. The models are further used for simulations of the behaviour of simple small-scale circuits including resonant tunnelling transistors. Examples of circuits studied are a monostable-bistable logic element and a ternary quantiser, where the later is based on a new 3D architecture of RTDs and VFETs},
  author       = {Wernersson, Lars-Erik and Lind, Erik and Lindström, Peter and Andreani, Pietro},
  isbn         = {0-7803-7448-7},
  keyword      = {VFETs,large signal models,Cadence simulation environment,DC I-V characteristics,monostable-bistable logic element,small-scale circuits,3D architecture,ternary quantiser,RTDs,resonant tunnelling permeable base transistors},
  language     = {eng},
  pages        = {205--208},
  publisher    = {ARRAY(0xa3b3f38)},
  series       = {2002 IEEE International Symposium on Circuits and Systems. Proceedings (Cat. No.02CH37353)},
  title        = {Circuits and devices with integrated VFETs and RTDs},
  url          = {http://dx.doi.org/10.1109/ISCAS.2002.1010676},
  year         = {2002},
}