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FPGA implementation of real-time image convolutions with three level of memory hierarchy

Jiang, Hongtu LU and Öwall, Viktor LU (2003) IEEE International Conference on Field-Programmable Technology (FPT) In [Host publication title missing] p.424-427
Abstract
In this paper, a customized image convolution processor with three level memory hierarchy is implemented on Xilinx VirtexE FPGAs. Due to its fully pipelined datapath for calculations and streamlined data flow architecture, the processor has the performance close to that of TI highest performance C64x processor at less than 1/8 of the clock frequency with substantial I/O bandwidth reductions. Furthermore, potential power savings are envisioned in future ASIC implementations by meaningful memory hierarchy explorations. In addition, a dedicated controller composed of Finite State Machine with incremental branch optimization architecture is developed to control all the operations in calculations and data transfer
Please use this url to cite or link to this publication:
author
organization
publishing date
type
Chapter in Book/Report/Conference proceeding
publication status
published
subject
keywords
field programmable gate arrays, FPGA implementation, real time image convolutions, memory hierarchy exploration, image convolution processor, finite state machine, application specific integrated circuits, incremental branch optimization, data transfer, control system synthesis, potential power savings, ASIC implementation, I/O bandwidth reduction, clock frequency, C64x processor, streamlined data flow, Xilinx VirtexE FPGA, pipelined datapath
in
[Host publication title missing]
pages
424 - 427
publisher
IEEE--Institute of Electrical and Electronics Engineers Inc.
conference name
IEEE International Conference on Field-Programmable Technology (FPT)
external identifiers
  • WOS:000189491800069
  • Scopus:33750216214
ISBN
0-7803-8320-6
DOI
10.1109/FPT.2003.1275793
language
English
LU publication?
yes
id
ced43eb1-dd05-4969-8fe1-2bc2c8a69606 (old id 612370)
date added to LUP
2007-11-28 15:16:39
date last changed
2016-10-13 04:46:21
@misc{ced43eb1-dd05-4969-8fe1-2bc2c8a69606,
  abstract     = {In this paper, a customized image convolution processor with three level memory hierarchy is implemented on Xilinx VirtexE FPGAs. Due to its fully pipelined datapath for calculations and streamlined data flow architecture, the processor has the performance close to that of TI highest performance C64x processor at less than 1/8 of the clock frequency with substantial I/O bandwidth reductions. Furthermore, potential power savings are envisioned in future ASIC implementations by meaningful memory hierarchy explorations. In addition, a dedicated controller composed of Finite State Machine with incremental branch optimization architecture is developed to control all the operations in calculations and data transfer},
  author       = {Jiang, Hongtu and Öwall, Viktor},
  isbn         = {0-7803-8320-6},
  keyword      = {field programmable gate arrays,FPGA implementation,real time image convolutions,memory hierarchy exploration,image convolution processor,finite state machine,application specific integrated circuits,incremental branch optimization,data transfer,control system synthesis,potential power savings,ASIC implementation,I/O bandwidth reduction,clock frequency,C64x processor,streamlined data flow,Xilinx VirtexE FPGA,pipelined datapath},
  language     = {eng},
  pages        = {424--427},
  publisher    = {ARRAY(0xa427968)},
  series       = {[Host publication title missing]},
  title        = {FPGA implementation of real-time image convolutions with three level of memory hierarchy},
  url          = {http://dx.doi.org/10.1109/FPT.2003.1275793},
  year         = {2003},
}