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Hardware accelerator design for video segmentation with multi-modal background modelling

Jiang, Hongtu LU ; Ardö, Håkan LU and Öwall, Viktor LU (2005) IEEE International Symposium on Circuits and Systems (ISCAS), 2005 In IEEE International Symposium on Circuits and Systems (ISCAS) p.1142-1145
Abstract
Among many of the algorithms for video segmentation, one based on a statistical background model (Stauffer, C. and Grimson, W., Proc. IEEE Conf. Computer Vision and Pattern Recognition, 1999) was developed with the unique feature of robustness in multi-modal background scenarios. However, with a large number of calculations due to the pixel-wise processing of each frame, such an algorithm could only achieve a low frame rate, far from real-time requirements, on computers. A hardware accelerator is proposed, with a dedicated architecture aimed at addressing both computation and memory bandwidth demands. The whole system is targeted to an FPGA platform, which serves as a real-time test bench where long term effects caused by fixed point... (More)
Among many of the algorithms for video segmentation, one based on a statistical background model (Stauffer, C. and Grimson, W., Proc. IEEE Conf. Computer Vision and Pattern Recognition, 1999) was developed with the unique feature of robustness in multi-modal background scenarios. However, with a large number of calculations due to the pixel-wise processing of each frame, such an algorithm could only achieve a low frame rate, far from real-time requirements, on computers. A hardware accelerator is proposed, with a dedicated architecture aimed at addressing both computation and memory bandwidth demands. The whole system is targeted to an FPGA platform, which serves as a real-time test bench where long term effects caused by fixed point quantization and various parameter settings can be studied. Meanwhile, memory bandwidth as well as memory size are investigated, and reduction by up to 60 percent, through similarity exploitation for neighboring Gaussian parameters, is envisioned. Furthermore, a controller synthesis tool is used to relieve the effort for the manual design of the complex control unit which schedules the operations of the whole system (Less)
Please use this url to cite or link to this publication:
author
organization
publishing date
type
Chapter in Book/Report/Conference proceeding
publication status
published
subject
keywords
similarity, video segmentation, hardware accelerator design, multi-modal background modelling, statistical background model, pixel-wise processing, computation demands, memory bandwidth demands, FPGA, fixed point quantization, real-time test bench, Gaussian distribution, scheduling, control unit, controller synthesis tool, Gaussian parameters
in
IEEE International Symposium on Circuits and Systems (ISCAS)
pages
1142 - 1145
publisher
IEEE--Institute of Electrical and Electronics Engineers Inc.
conference name
IEEE International Symposium on Circuits and Systems (ISCAS), 2005
external identifiers
  • WOS:000232002401075
  • Scopus:67649105973
ISBN
0-7803-8834-8
DOI
10.1109/ISCAS.2005.1464795
language
English
LU publication?
yes
id
2ff454e9-eb74-4e23-a11b-68569e83f0ea (old id 615799)
date added to LUP
2007-11-25 11:45:44
date last changed
2016-10-30 04:41:31
@misc{2ff454e9-eb74-4e23-a11b-68569e83f0ea,
  abstract     = {Among many of the algorithms for video segmentation, one based on a statistical background model (Stauffer, C. and Grimson, W., Proc. IEEE Conf. Computer Vision and Pattern Recognition, 1999) was developed with the unique feature of robustness in multi-modal background scenarios. However, with a large number of calculations due to the pixel-wise processing of each frame, such an algorithm could only achieve a low frame rate, far from real-time requirements, on computers. A hardware accelerator is proposed, with a dedicated architecture aimed at addressing both computation and memory bandwidth demands. The whole system is targeted to an FPGA platform, which serves as a real-time test bench where long term effects caused by fixed point quantization and various parameter settings can be studied. Meanwhile, memory bandwidth as well as memory size are investigated, and reduction by up to 60 percent, through similarity exploitation for neighboring Gaussian parameters, is envisioned. Furthermore, a controller synthesis tool is used to relieve the effort for the manual design of the complex control unit which schedules the operations of the whole system},
  author       = {Jiang, Hongtu and Ardö, Håkan and Öwall, Viktor},
  isbn         = {0-7803-8834-8},
  keyword      = {similarity,video segmentation,hardware accelerator design,multi-modal background modelling,statistical background model,pixel-wise processing,computation demands,memory bandwidth demands,FPGA,fixed point quantization,real-time test bench,Gaussian distribution,scheduling,control unit,controller synthesis tool,Gaussian parameters},
  language     = {eng},
  pages        = {1142--1145},
  publisher    = {ARRAY(0x78aa4f0)},
  series       = {IEEE International Symposium on Circuits and Systems (ISCAS)},
  title        = {Hardware accelerator design for video segmentation with multi-modal background modelling},
  url          = {http://dx.doi.org/10.1109/ISCAS.2005.1464795},
  year         = {2005},
}