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A scalable pipelined complex valued matrix inversion architecture

Edman, F and Öwall, Viktor LU (2005) IEEE International Symposium on Circuits and Systems (ISCAS), 2005 In IEEE International Symposium on Circuits and Systems (ISCAS) p.4489-4492
Abstract
This paper presents a fast, pipelined and scalable hardware architecture for inverting complex valued matrices. The matrix inversion algorithm involves, a QR-factorization based on the squared Givens rotations algorithm, the application of a recurrence algorithm for inversion of an upper triangular matrix R, and a matrix multiplication of R<sup>-1</sup> with Q. We show that traditional triangular array architectures employing O(n<sup>2</sup>) communicating processors can be mapped onto a scalable linear array architecture with only O(n) processors. The linear array architecture avoids drawbacks such as non-scalability, large area consumption and low throughput rate. The architecture is implemented using arithmetic... (More)
This paper presents a fast, pipelined and scalable hardware architecture for inverting complex valued matrices. The matrix inversion algorithm involves, a QR-factorization based on the squared Givens rotations algorithm, the application of a recurrence algorithm for inversion of an upper triangular matrix R, and a matrix multiplication of R<sup>-1</sup> with Q. We show that traditional triangular array architectures employing O(n<sup>2</sup>) communicating processors can be mapped onto a scalable linear array architecture with only O(n) processors. The linear array architecture avoids drawbacks such as non-scalability, large area consumption and low throughput rate. The architecture is implemented using arithmetic operations with 12 bit fixed-point representation. The hardware implementation will be used as a core processor in a real-time smart antenna system (Less)
Please use this url to cite or link to this publication:
author
organization
publishing date
type
Chapter in Book/Report/Conference proceeding
publication status
published
subject
keywords
squared Givens rotations algorithm, recurrence algorithm, triangular matrix, linear array architecture, smart antenna systems, fixed-point representation arithmetic operations, 12 bit, QR-factorization, complex valued matrix inversion, FPGA implementation, scalable pipelined architecture
in
IEEE International Symposium on Circuits and Systems (ISCAS)
pages
4489 - 4492
publisher
IEEE--Institute of Electrical and Electronics Engineers Inc.
conference name
IEEE International Symposium on Circuits and Systems (ISCAS), 2005
external identifiers
  • WOS:000232002404079
  • Scopus:49149097777
ISBN
0-7803-8834-8
DOI
10.1109/ISCAS.2005.1465629
language
English
LU publication?
yes
id
97b86b64-c937-411b-a3ab-1858bacc0535 (old id 616135)
date added to LUP
2007-11-25 09:54:31
date last changed
2016-10-13 04:40:04
@misc{97b86b64-c937-411b-a3ab-1858bacc0535,
  abstract     = {This paper presents a fast, pipelined and scalable hardware architecture for inverting complex valued matrices. The matrix inversion algorithm involves, a QR-factorization based on the squared Givens rotations algorithm, the application of a recurrence algorithm for inversion of an upper triangular matrix R, and a matrix multiplication of R&lt;sup&gt;-1&lt;/sup&gt; with Q. We show that traditional triangular array architectures employing O(n&lt;sup&gt;2&lt;/sup&gt;) communicating processors can be mapped onto a scalable linear array architecture with only O(n) processors. The linear array architecture avoids drawbacks such as non-scalability, large area consumption and low throughput rate. The architecture is implemented using arithmetic operations with 12 bit fixed-point representation. The hardware implementation will be used as a core processor in a real-time smart antenna system},
  author       = {Edman, F and Öwall, Viktor},
  isbn         = {0-7803-8834-8},
  keyword      = {squared Givens rotations algorithm,recurrence algorithm,triangular matrix,linear array architecture,smart antenna systems,fixed-point representation arithmetic operations,12 bit,QR-factorization,complex valued matrix inversion,FPGA implementation,scalable pipelined architecture},
  language     = {eng},
  pages        = {4489--4492},
  publisher    = {ARRAY(0x9ac8920)},
  series       = {IEEE International Symposium on Circuits and Systems (ISCAS)},
  title        = {A scalable pipelined complex valued matrix inversion architecture},
  url          = {http://dx.doi.org/10.1109/ISCAS.2005.1465629},
  year         = {2005},
}