A scalable pipelined complex valued matrix inversion architecture
(2005) IEEE International Symposium on Circuits and Systems (ISCAS), 2005 In IEEE International Symposium on Circuits and Systems (ISCAS) p.44894492 Abstract
 This paper presents a fast, pipelined and scalable hardware architecture for inverting complex valued matrices. The matrix inversion algorithm involves, a QRfactorization based on the squared Givens rotations algorithm, the application of a recurrence algorithm for inversion of an upper triangular matrix R, and a matrix multiplication of R<sup>1</sup> with Q. We show that traditional triangular array architectures employing O(n<sup>2</sup>) communicating processors can be mapped onto a scalable linear array architecture with only O(n) processors. The linear array architecture avoids drawbacks such as nonscalability, large area consumption and low throughput rate. The architecture is implemented using arithmetic... (More)
 This paper presents a fast, pipelined and scalable hardware architecture for inverting complex valued matrices. The matrix inversion algorithm involves, a QRfactorization based on the squared Givens rotations algorithm, the application of a recurrence algorithm for inversion of an upper triangular matrix R, and a matrix multiplication of R<sup>1</sup> with Q. We show that traditional triangular array architectures employing O(n<sup>2</sup>) communicating processors can be mapped onto a scalable linear array architecture with only O(n) processors. The linear array architecture avoids drawbacks such as nonscalability, large area consumption and low throughput rate. The architecture is implemented using arithmetic operations with 12 bit fixedpoint representation. The hardware implementation will be used as a core processor in a realtime smart antenna system (Less)
Please use this url to cite or link to this publication:
http://lup.lub.lu.se/record/616135
 author
 Edman, F and Öwall, Viktor ^{LU}
 organization
 publishing date
 2005
 type
 Chapter in Book/Report/Conference proceeding
 publication status
 published
 subject
 keywords
 squared Givens rotations algorithm, recurrence algorithm, triangular matrix, linear array architecture, smart antenna systems, fixedpoint representation arithmetic operations, 12 bit, QRfactorization, complex valued matrix inversion, FPGA implementation, scalable pipelined architecture
 in
 IEEE International Symposium on Circuits and Systems (ISCAS)
 pages
 4489  4492
 publisher
 IEEEInstitute of Electrical and Electronics Engineers Inc.
 conference name
 IEEE International Symposium on Circuits and Systems (ISCAS), 2005
 external identifiers

 WOS:000232002404079
 Scopus:49149097777
 ISBN
 0780388348
 DOI
 10.1109/ISCAS.2005.1465629
 language
 English
 LU publication?
 yes
 id
 97b86b64c937411ba3ab1858bacc0535 (old id 616135)
 date added to LUP
 20071125 09:54:31
 date last changed
 20161013 04:40:04
@misc{97b86b64c937411ba3ab1858bacc0535, abstract = {This paper presents a fast, pipelined and scalable hardware architecture for inverting complex valued matrices. The matrix inversion algorithm involves, a QRfactorization based on the squared Givens rotations algorithm, the application of a recurrence algorithm for inversion of an upper triangular matrix R, and a matrix multiplication of R<sup>1</sup> with Q. We show that traditional triangular array architectures employing O(n<sup>2</sup>) communicating processors can be mapped onto a scalable linear array architecture with only O(n) processors. The linear array architecture avoids drawbacks such as nonscalability, large area consumption and low throughput rate. The architecture is implemented using arithmetic operations with 12 bit fixedpoint representation. The hardware implementation will be used as a core processor in a realtime smart antenna system}, author = {Edman, F and Öwall, Viktor}, isbn = {0780388348}, keyword = {squared Givens rotations algorithm,recurrence algorithm,triangular matrix,linear array architecture,smart antenna systems,fixedpoint representation arithmetic operations,12 bit,QRfactorization,complex valued matrix inversion,FPGA implementation,scalable pipelined architecture}, language = {eng}, pages = {44894492}, publisher = {ARRAY(0x9dbd3b0)}, series = {IEEE International Symposium on Circuits and Systems (ISCAS)}, title = {A scalable pipelined complex valued matrix inversion architecture}, url = {http://dx.doi.org/10.1109/ISCAS.2005.1465629}, year = {2005}, }