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A low-power 8-bit folding A/D converter with improved accuracy

Chen, Cheng and Yuan, Jiren LU (2006) 2006 8th International Conference on Solid-State and Integrated Circuit Technology In 2006 8th International Conference on Solid-State and Integrated Circuit Technology
Abstract
In this paper, an accuracy improving method for calibration of mismatch-induced errors in folding A/D converter is presented. With dynamic auto-zero calibration for the folder, the transistor size of folding differential input pairs can be reduced considerably while keeping integral nonlinearity (INL) low. Using this technique, an 8-bit folding A/D converter is designed and simulated in MATLAB. Because of the calibration, conventional preamplifiers and offset averaging network before the folders are removed, saving a large power consumption and chip area. Results are demonstrated, showing the improved accuracy and the good agreement with the theoretical prediction
Please use this url to cite or link to this publication:
author
organization
publishing date
type
Chapter in Book/Report/Conference proceeding
publication status
published
subject
keywords
analog-digital converter, folding A/D converter, folding differential input, dynamic auto-zero calibration, MATLAB, 8 bit, integral nonlinearity
in
2006 8th International Conference on Solid-State and Integrated Circuit Technology
pages
4 pages
publisher
IEEE--Institute of Electrical and Electronics Engineers Inc.
conference name
2006 8th International Conference on Solid-State and Integrated Circuit Technology
external identifiers
  • Scopus:34547300027
ISBN
1-4244-0160-7
DOI
10.1109/ICSICT.2006.306375
language
English
LU publication?
yes
id
d1313c0b-51e7-4bbd-9dfe-a21b9563425a (old id 616785)
date added to LUP
2007-11-24 09:44:37
date last changed
2016-10-13 04:42:24
@misc{d1313c0b-51e7-4bbd-9dfe-a21b9563425a,
  abstract     = {In this paper, an accuracy improving method for calibration of mismatch-induced errors in folding A/D converter is presented. With dynamic auto-zero calibration for the folder, the transistor size of folding differential input pairs can be reduced considerably while keeping integral nonlinearity (INL) low. Using this technique, an 8-bit folding A/D converter is designed and simulated in MATLAB. Because of the calibration, conventional preamplifiers and offset averaging network before the folders are removed, saving a large power consumption and chip area. Results are demonstrated, showing the improved accuracy and the good agreement with the theoretical prediction},
  author       = {Chen, Cheng and Yuan, Jiren},
  isbn         = {1-4244-0160-7},
  keyword      = {analog-digital converter,folding A/D converter,folding differential input,dynamic auto-zero calibration,MATLAB,8 bit,integral nonlinearity},
  language     = {eng},
  pages        = {4},
  publisher    = {ARRAY(0xb23fc88)},
  series       = {2006 8th International Conference on Solid-State and Integrated Circuit Technology},
  title        = {A low-power 8-bit folding A/D converter with improved accuracy},
  url          = {http://dx.doi.org/10.1109/ICSICT.2006.306375},
  year         = {2006},
}