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Second Harmonic 60-GHz Power Amplifiers in 130-nm CMOS

Wernehag, Johan LU and Sjöland, Henrik LU (2007) IEEE Ph. D. Research in Microelectronics and Electronics In Proceeding of IEEE Ph. D. Research in Microelectronics and Electronics p.149-152
Abstract
Two different frequency doubling power amplifier topologies have been compared, one with differential input and one with single-ended, both with single-ended output at 60 GHz. The frequency doubling capability is valuable from at least two perspectives, 1) the high frequency signal is on the chip as little as possible 2) the voltage controlled oscillator and power amplifier are at different frequencies easing the isolation of the two in a transceiver. The topologies have been simulated in a 1p8M 130-nm CMOS process. The resonant nodes are tuned with on-chip transmission lines. These have been simulated in ADS and compared to a standard Cadence component, tline3. The Cadence component gives a somewhat pessimistic estimation of the losses in... (More)
Two different frequency doubling power amplifier topologies have been compared, one with differential input and one with single-ended, both with single-ended output at 60 GHz. The frequency doubling capability is valuable from at least two perspectives, 1) the high frequency signal is on the chip as little as possible 2) the voltage controlled oscillator and power amplifier are at different frequencies easing the isolation of the two in a transceiver. The topologies have been simulated in a 1p8M 130-nm CMOS process. The resonant nodes are tuned with on-chip transmission lines. These have been simulated in ADS and compared to a standard Cadence component, tline3. The Cadence component gives a somewhat pessimistic estimation of the losses in the transmission line. The single ended input amplifier outputs a maximum of 3.7 dBm and draws 27 mA from a 1.2 V supply, while the one with differential input outputs 5.0 dBm and draws 28 mA. The 3-dB bandwidth of the amplifiers are 5.9 GHz and 6.8 GHz, respectively. (Less)
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author
organization
publishing date
type
Chapter in Book/Report/Conference proceeding
publication status
published
subject
in
Proceeding of IEEE Ph. D. Research in Microelectronics and Electronics
pages
4 pages
publisher
IEEE--Institute of Electrical and Electronics Engineers Inc.
conference name
IEEE Ph. D. Research in Microelectronics and Electronics
external identifiers
  • WOS:000255548900038
  • Scopus:47349118018
language
English
LU publication?
yes
id
79cdccc1-2b14-485f-b042-b80a5b9bd634 (old id 621388)
date added to LUP
2007-12-12 12:25:32
date last changed
2016-10-13 04:38:04
@misc{79cdccc1-2b14-485f-b042-b80a5b9bd634,
  abstract     = {Two different frequency doubling power amplifier topologies have been compared, one with differential input and one with single-ended, both with single-ended output at 60 GHz. The frequency doubling capability is valuable from at least two perspectives, 1) the high frequency signal is on the chip as little as possible 2) the voltage controlled oscillator and power amplifier are at different frequencies easing the isolation of the two in a transceiver. The topologies have been simulated in a 1p8M 130-nm CMOS process. The resonant nodes are tuned with on-chip transmission lines. These have been simulated in ADS and compared to a standard Cadence component, tline3. The Cadence component gives a somewhat pessimistic estimation of the losses in the transmission line. The single ended input amplifier outputs a maximum of 3.7 dBm and draws 27 mA from a 1.2 V supply, while the one with differential input outputs 5.0 dBm and draws 28 mA. The 3-dB bandwidth of the amplifiers are 5.9 GHz and 6.8 GHz, respectively.},
  author       = {Wernehag, Johan and Sjöland, Henrik},
  language     = {eng},
  pages        = {149--152},
  publisher    = {ARRAY(0x7fe6960)},
  series       = {Proceeding of IEEE Ph. D. Research in Microelectronics and Electronics},
  title        = {Second Harmonic 60-GHz Power Amplifiers in 130-nm CMOS},
  year         = {2007},
}