Advanced

A New Rounding Method Based on Parallel Remainder Estimation for Goldschmidt and Newton-Raphson Algorithms

Piso Fernandez, Daniel LU and Bruguera, Javier D. (2014) 17th Euromicro Conference on Digital System Design (DSD) In 2014 17th Euromicro Conference on Digital System Design (Dsd) p.639-642
Abstract
Newton-Raphson and Goldschmidt algorithms can be sped up by using variable latency hardware architectures for rounding division, square root and their reciprocals. A new approach based on a rounding method with remainder estimate calculated concurrently with the algorithm was proposed in [5]. This paper presents an study of the hardware implementation of this approach and shows that does not suppose additional latency and avoids conventional remainder calculation most of the times. By using a CMOS 90 nm technology library different hardware architectures are presented. The results show that the expected performance improvements are obtained with reasonable increments in area (up to 5.6%), critical path (up to 6.7%) and better power... (More)
Newton-Raphson and Goldschmidt algorithms can be sped up by using variable latency hardware architectures for rounding division, square root and their reciprocals. A new approach based on a rounding method with remainder estimate calculated concurrently with the algorithm was proposed in [5]. This paper presents an study of the hardware implementation of this approach and shows that does not suppose additional latency and avoids conventional remainder calculation most of the times. By using a CMOS 90 nm technology library different hardware architectures are presented. The results show that the expected performance improvements are obtained with reasonable increments in area (up to 5.6%), critical path (up to 6.7%) and better power performance (up to -24%). (Less)
Please use this url to cite or link to this publication:
author
organization
publishing date
type
Chapter in Book/Report/Conference proceeding
publication status
published
subject
in
2014 17th Euromicro Conference on Digital System Design (Dsd)
pages
639 - 642
publisher
IEEE--Institute of Electrical and Electronics Engineers Inc.
conference name
17th Euromicro Conference on Digital System Design (DSD)
external identifiers
  • WOS:000358409000084
  • Scopus:84928812635
DOI
10.1109/DSD.2014.23
language
English
LU publication?
yes
id
379520d7-3627-4407-8579-95c65ab3afb3 (old id 7773596)
date added to LUP
2015-09-07 13:40:01
date last changed
2016-10-13 04:37:46
@misc{379520d7-3627-4407-8579-95c65ab3afb3,
  abstract     = {Newton-Raphson and Goldschmidt algorithms can be sped up by using variable latency hardware architectures for rounding division, square root and their reciprocals. A new approach based on a rounding method with remainder estimate calculated concurrently with the algorithm was proposed in [5]. This paper presents an study of the hardware implementation of this approach and shows that does not suppose additional latency and avoids conventional remainder calculation most of the times. By using a CMOS 90 nm technology library different hardware architectures are presented. The results show that the expected performance improvements are obtained with reasonable increments in area (up to 5.6%), critical path (up to 6.7%) and better power performance (up to -24%).},
  author       = {Piso Fernandez, Daniel and Bruguera, Javier D.},
  language     = {eng},
  pages        = {639--642},
  publisher    = {ARRAY(0xb8065b0)},
  series       = {2014 17th Euromicro Conference on Digital System Design (Dsd)},
  title        = {A New Rounding Method Based on Parallel Remainder Estimation for Goldschmidt and Newton-Raphson Algorithms},
  url          = {http://dx.doi.org/10.1109/DSD.2014.23},
  year         = {2014},
}