A New Rounding Method Based on Parallel Remainder Estimation for Goldschmidt and Newton-Raphson Algorithms
(2014) 17th Euromicro Conference on Digital System Design (DSD) p.639-642- Abstract
- Newton-Raphson and Goldschmidt algorithms can be sped up by using variable latency hardware architectures for rounding division, square root and their reciprocals. A new approach based on a rounding method with remainder estimate calculated concurrently with the algorithm was proposed in [5]. This paper presents an study of the hardware implementation of this approach and shows that does not suppose additional latency and avoids conventional remainder calculation most of the times. By using a CMOS 90 nm technology library different hardware architectures are presented. The results show that the expected performance improvements are obtained with reasonable increments in area (up to 5.6%), critical path (up to 6.7%) and better power... (More)
- Newton-Raphson and Goldschmidt algorithms can be sped up by using variable latency hardware architectures for rounding division, square root and their reciprocals. A new approach based on a rounding method with remainder estimate calculated concurrently with the algorithm was proposed in [5]. This paper presents an study of the hardware implementation of this approach and shows that does not suppose additional latency and avoids conventional remainder calculation most of the times. By using a CMOS 90 nm technology library different hardware architectures are presented. The results show that the expected performance improvements are obtained with reasonable increments in area (up to 5.6%), critical path (up to 6.7%) and better power performance (up to -24%). (Less)
Please use this url to cite or link to this publication:
https://lup.lub.lu.se/record/7773596
- author
- Piso Fernandez, Daniel LU and Bruguera, Javier D.
- organization
- publishing date
- 2014
- type
- Chapter in Book/Report/Conference proceeding
- publication status
- published
- subject
- host publication
- 2014 17th Euromicro Conference on Digital System Design (Dsd)
- pages
- 639 - 642
- publisher
- IEEE - Institute of Electrical and Electronics Engineers Inc.
- conference name
- 17th Euromicro Conference on Digital System Design (DSD)
- conference dates
- 2014-08-27 - 2014-08-29
- external identifiers
-
- wos:000358409000084
- scopus:84928812635
- DOI
- 10.1109/DSD.2014.23
- language
- English
- LU publication?
- yes
- id
- 379520d7-3627-4407-8579-95c65ab3afb3 (old id 7773596)
- date added to LUP
- 2016-04-04 10:03:52
- date last changed
- 2022-01-29 19:42:53
@inproceedings{379520d7-3627-4407-8579-95c65ab3afb3,
abstract = {{Newton-Raphson and Goldschmidt algorithms can be sped up by using variable latency hardware architectures for rounding division, square root and their reciprocals. A new approach based on a rounding method with remainder estimate calculated concurrently with the algorithm was proposed in [5]. This paper presents an study of the hardware implementation of this approach and shows that does not suppose additional latency and avoids conventional remainder calculation most of the times. By using a CMOS 90 nm technology library different hardware architectures are presented. The results show that the expected performance improvements are obtained with reasonable increments in area (up to 5.6%), critical path (up to 6.7%) and better power performance (up to -24%).}},
author = {{Piso Fernandez, Daniel and Bruguera, Javier D.}},
booktitle = {{2014 17th Euromicro Conference on Digital System Design (Dsd)}},
language = {{eng}},
pages = {{639--642}},
publisher = {{IEEE - Institute of Electrical and Electronics Engineers Inc.}},
title = {{A New Rounding Method Based on Parallel Remainder Estimation for Goldschmidt and Newton-Raphson Algorithms}},
url = {{http://dx.doi.org/10.1109/DSD.2014.23}},
doi = {{10.1109/DSD.2014.23}},
year = {{2014}},
}