Ultra low energy and area efficient charge pump with automatic clock controller in 65 nm CMOS
(2016) 11th IEEE Asian Solid-State Circuits Conference, A-SSCC 2015- Abstract
A low power CMOS charge pump (CP) is proposed utilizing a new combination of charge transferring switches for a faster start-up, higher efficiency and lower reverse charge sharing. A low cost feedback mechanism observes the output voltage level and automatically switches off the clock after passing a threshold, which reduces energy dissipation by 62%. It is shown that by using one capacitor per stage, the proposed architecture reaches higher voltages compared to the competitive architectures when driving capacitive loads. The design is manufactured in a 65 nm technology, and measurement results confirm a 120% higher voltage compared to the conventional Dickson CP at 400 mV with identical area cost. The measured minimum operating voltage... (More)
A low power CMOS charge pump (CP) is proposed utilizing a new combination of charge transferring switches for a faster start-up, higher efficiency and lower reverse charge sharing. A low cost feedback mechanism observes the output voltage level and automatically switches off the clock after passing a threshold, which reduces energy dissipation by 62%. It is shown that by using one capacitor per stage, the proposed architecture reaches higher voltages compared to the competitive architectures when driving capacitive loads. The design is manufactured in a 65 nm technology, and measurement results confirm a 120% higher voltage compared to the conventional Dickson CP at 400 mV with identical area cost. The measured minimum operating voltage and highest charge pumping efficiency are 290 mV and 86%, respectively.
(Less)
- author
- Mohammadi, Babak LU and Rodrigues, Joachim LU
- organization
- publishing date
- 2016-01-19
- type
- Chapter in Book/Report/Conference proceeding
- publication status
- published
- subject
- host publication
- 2015 IEEE Asian Solid-State Circuits Conference, A-SSCC 2015 - Proceedings
- article number
- 7387491
- publisher
- IEEE - Institute of Electrical and Electronics Engineers Inc.
- conference name
- 11th IEEE Asian Solid-State Circuits Conference, A-SSCC 2015
- conference location
- Xiamen, Fujian, China
- conference dates
- 2015-11-09 - 2015-11-11
- external identifiers
-
- scopus:84963813641
- ISBN
- 9781467371919
- DOI
- 10.1109/ASSCC.2015.7387491
- language
- English
- LU publication?
- yes
- id
- 7f9d4482-3c30-48c2-aa19-e84d46ce2176
- date added to LUP
- 2016-06-16 09:47:36
- date last changed
- 2022-04-08 21:33:27
@inproceedings{7f9d4482-3c30-48c2-aa19-e84d46ce2176,
abstract = {{<p>A low power CMOS charge pump (CP) is proposed utilizing a new combination of charge transferring switches for a faster start-up, higher efficiency and lower reverse charge sharing. A low cost feedback mechanism observes the output voltage level and automatically switches off the clock after passing a threshold, which reduces energy dissipation by 62%. It is shown that by using one capacitor per stage, the proposed architecture reaches higher voltages compared to the competitive architectures when driving capacitive loads. The design is manufactured in a 65 nm technology, and measurement results confirm a 120% higher voltage compared to the conventional Dickson CP at 400 mV with identical area cost. The measured minimum operating voltage and highest charge pumping efficiency are 290 mV and 86%, respectively.</p>}},
author = {{Mohammadi, Babak and Rodrigues, Joachim}},
booktitle = {{2015 IEEE Asian Solid-State Circuits Conference, A-SSCC 2015 - Proceedings}},
isbn = {{9781467371919}},
language = {{eng}},
month = {{01}},
publisher = {{IEEE - Institute of Electrical and Electronics Engineers Inc.}},
title = {{Ultra low energy and area efficient charge pump with automatic clock controller in 65 nm CMOS}},
url = {{http://dx.doi.org/10.1109/ASSCC.2015.7387491}},
doi = {{10.1109/ASSCC.2015.7387491}},
year = {{2016}},
}