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Vertical III-V/High-k Nanowire MOS Capacitors and Transistors

Wu, Jun LU (2016) In Lund University Ph.D. thesis
Abstract (Swedish)
Popular Abstract in English

Since 1947 when the first transistor was invented, electronics was transited into an unprecedented era. Different from a resistor that only has two terminals with the applied voltage and flowing current always obeying Ohm's law, a transistor has the third terminal in between, called "gate", which is made by, for metal-oxide-semiconductor field effect transistors (MOSFETs), an oxide layer sandwiched between the metal electrode and the semiconductor channel. This terminal can control the current flowing through the semiconductor by creating an electrical field in the channel when a voltage is applied, hence realizing the switching function between digital 1 (switching on with current flowing) and... (More)
Popular Abstract in English

Since 1947 when the first transistor was invented, electronics was transited into an unprecedented era. Different from a resistor that only has two terminals with the applied voltage and flowing current always obeying Ohm's law, a transistor has the third terminal in between, called "gate", which is made by, for metal-oxide-semiconductor field effect transistors (MOSFETs), an oxide layer sandwiched between the metal electrode and the semiconductor channel. This terminal can control the current flowing through the semiconductor by creating an electrical field in the channel when a voltage is applied, hence realizing the switching function between digital 1 (switching on with current flowing) and digital 0 (switching off with current blocked). This is the basis of all digital calculations, and, hence, all modern computers. Besides, a small voltage variation (input signal) sent to the gate node can create a large variation in current in the channel (output signal) under some conditions, which realizes, on the other hand, the signal amplification function. This is the basis of all analogue applications, and, hence, all modern mobile phones.



Based on the transistor technology, the first integrated circuit (IC) was invented in 1960s, which was another revolutionary creation of that century. In an IC, many transistors are integrated in the semiconductor material of silicon to realize different digital and analog functions. The co-founder of Intel, Gordon Moore, predicted in 1965 that the number of transistors per chip would double every 24 months. This prediction later was called Moore's law, and it was accurately followed during the last 50 years via the continuous transistor size downscaling. It also became one of the main goals of the semiconductor industry, since reducing the transistor size not only resulted in an increased packing density of modern ICs and a reduced fabrication cost per transistor, but also an increased circuit speed and a reduced power consumption as the transistor gate length was reduced continuously.



The transistor size downscaling, however, is not a permanent strategy unfortunately, since as the transistor gate length is reduced below several tens nanometers. The gate will lose control of the channel charges, which is usually termed "short channel effects". After 2002, people began to seek alternative solutions to continuously increase the IC performance. One of the most promising solutions, which is also the main topic of the thesis, was the vertical warp-gated indium arsenide (InAs)/high-k oxide nanowire MOSFETs. The vertical nanowire geometry enables gate electrode surrounding the nanowire, i.e. warp-gated, as compared with the conventional planar MOSFET technique. Thus electric field can be applied from all directions, leading to more efficient gate control. Besides the use of InAs provides high mobility charge carriers, which means that the charges can transport faster than those in Si under the same voltage bias. In addition, the use of high-k oxide in the gate leads to larger gate capacitance, which also increases the gate efficiency.



Challenges also exist, however, for the new candidate. From the material's point of view, the interface between the high-k oxide and the semiconductor turns out to be a key to success, since defects at this interface will influence the charge control inside the semiconductor significantly, which is also one of the most severe hindrances of the technology so far.



This work presents the development of a reliable technique to study the vertical wrap-gated nanowire gate stack, understanding and improvement of the gate performance of this type of MOSFETs. Besides, the thesis also presents a new vertical nanowire transistor design with further improved performance. In addition, a vertical integration scheme was developed, where track-and-hold circuits, consisting of a MOSFET in series with a metal-insulator-metal capacitor, were successfully fabricated along vertical InAs nanowires. (Less)
Abstract
The emerging nanowire technology in recent years has attracted an increasing interest for high-speed, low-power electronics due to the possibility of a gate-all-around (GAA) geometry enabling aggressive gate length scaling, together with the ease in incorporating high-mobility narrow band gap III-V semiconductors such as InAs on Si substrates. These benefits make vertical nanowire transistors an attractive alternative to the planar devices. However, huge challenges are also encountered. Apart from the large parasitics associated with the device layout, vertical III-V/high-k nanowire MOSFETs so far are also suffering from a less efficient gate control partially due to the defect states existing in the MOS gate stack. Besides the narrow band... (More)
The emerging nanowire technology in recent years has attracted an increasing interest for high-speed, low-power electronics due to the possibility of a gate-all-around (GAA) geometry enabling aggressive gate length scaling, together with the ease in incorporating high-mobility narrow band gap III-V semiconductors such as InAs on Si substrates. These benefits make vertical nanowire transistors an attractive alternative to the planar devices. However, huge challenges are also encountered. Apart from the large parasitics associated with the device layout, vertical III-V/high-k nanowire MOSFETs so far are also suffering from a less efficient gate control partially due to the defect states existing in the MOS gate stack. Besides the narrow band gap InAs may result in impact-ionization and band-to-band tunneling at high drain voltages, influencing both the power efficiency and speed of modern integrated circuits (ICs).



In this thesis, results on planar InAs/high-k MOS gate stacks investigated in detail using both the capacitance-voltage (C-V) and the x-ray photoelectron spectroscopy (XPS) techniques are first presented (Paper I and II). The origin of the specific trap state energy distribution is clarified and compared to the well studied InGaAs and GaAs materials. The results highlight the benefit of using InAs, with optimized high-k deposition strategies, as the n-MOSFET channel.



The second focus of the thesis is the improvement of vertical GAA nanowire MOS gate stacks (Paper III and IV). By developing the fabrication scheme and design, conventional C-V technique is successfully applied to extract detailed trap state distributions. A low interface trap state density (Dit) below 10E12 eV-1cm-2 near the MOS semiconductor conduction band edge is achieved. Furthermore, RF C-V measurements, together with the development of a complete small signal equivalent circuit model, for vertical GAA nanowire MOS systems are also presented for the first time, which enables characterizations of border trap density, interface trap density, channel resistivity and quality factor of the nanowire MOSFETs simultaneously.



The third focus is the development of a device structure to reduce detrimental impact-ionization and band-to-band tunneling due to the narrow band gap of InAs (Paper V and VI). An asymmetric InAs/InGaAs vertical nanowire MOSFET with a large band gap drain region is proposed, taking advantage of the efficient strain relaxation of nanowire epitaxial growth. Control of the InGaAs nanowire composition has been successfully demonstrated.



Finally, a vertical integration scheme was developed in the thesis, where track-and-hold circuits, consisting of a MOSFET in series with a metal-insulator-metal capacitor, were successfully fabricated along vertical InAs nanowires (Paper VII). (Less)
Please use this url to cite or link to this publication:
author
supervisor
opponent
  • Associate Professor Hinkle, Chris, Department of Material Science and Engineering, University of Texas at Dallas
organization
publishing date
type
Thesis
publication status
published
subject
keywords
Nanowire, MOSFET, MOS capacitor, C-V, XPS, MOVPE, InGaAs, InAs, High-k, RF, Track-and-hold circuit
in
Lund University Ph.D. thesis
pages
100 pages
publisher
Department of Electrical and Information Technology, Lund University
defense location
Lecture hall E:1406, building E, Ole Römers väg 3, Lund University, Faculty of Engineering LTH, Lund
defense date
2016-04-22 13:15
ISBN
978-91-7623-681-9
language
English
LU publication?
yes
id
3c3dff14-9d1d-4a1a-bc37-a2d250d75a35 (old id 8865209)
date added to LUP
2016-03-22 10:26:11
date last changed
2016-09-19 08:45:15
@misc{3c3dff14-9d1d-4a1a-bc37-a2d250d75a35,
  abstract     = {The emerging nanowire technology in recent years has attracted an increasing interest for high-speed, low-power electronics due to the possibility of a gate-all-around (GAA) geometry enabling aggressive gate length scaling, together with the ease in incorporating high-mobility narrow band gap III-V semiconductors such as InAs on Si substrates. These benefits make vertical nanowire transistors an attractive alternative to the planar devices. However, huge challenges are also encountered. Apart from the large parasitics associated with the device layout, vertical III-V/high-k nanowire MOSFETs so far are also suffering from a less efficient gate control partially due to the defect states existing in the MOS gate stack. Besides the narrow band gap InAs may result in impact-ionization and band-to-band tunneling at high drain voltages, influencing both the power efficiency and speed of modern integrated circuits (ICs). <br/><br>
<br/><br>
In this thesis, results on planar InAs/high-k MOS gate stacks investigated in detail using both the capacitance-voltage (C-V) and the x-ray photoelectron spectroscopy (XPS) techniques are first presented (Paper I and II). The origin of the specific trap state energy distribution is clarified and compared to the well studied InGaAs and GaAs materials. The results highlight the benefit of using InAs, with optimized high-k deposition strategies, as the n-MOSFET channel. <br/><br>
<br/><br>
The second focus of the thesis is the improvement of vertical GAA nanowire MOS gate stacks (Paper III and IV). By developing the fabrication scheme and design, conventional C-V technique is successfully applied to extract detailed trap state distributions. A low interface trap state density (Dit) below 10E12 eV-1cm-2 near the MOS semiconductor conduction band edge is achieved. Furthermore, RF C-V measurements, together with the development of a complete small signal equivalent circuit model, for vertical GAA nanowire MOS systems are also presented for the first time, which enables characterizations of border trap density, interface trap density, channel resistivity and quality factor of the nanowire MOSFETs simultaneously. <br/><br>
<br/><br>
The third focus is the development of a device structure to reduce detrimental impact-ionization and band-to-band tunneling due to the narrow band gap of InAs (Paper V and VI). An asymmetric InAs/InGaAs vertical nanowire MOSFET with a large band gap drain region is proposed, taking advantage of the efficient strain relaxation of nanowire epitaxial growth. Control of the InGaAs nanowire composition has been successfully demonstrated.<br/><br>
<br/><br>
Finally, a vertical integration scheme was developed in the thesis, where track-and-hold circuits, consisting of a MOSFET in series with a metal-insulator-metal capacitor, were successfully fabricated along vertical InAs nanowires (Paper VII).},
  author       = {Wu, Jun},
  isbn         = {978-91-7623-681-9},
  keyword      = {Nanowire,MOSFET,MOS capacitor,C-V,XPS,MOVPE,InGaAs,InAs,High-k,RF,Track-and-hold circuit},
  language     = {eng},
  pages        = {100},
  publisher    = {ARRAY(0x9710e20)},
  series       = {Lund University Ph.D. thesis},
  title        = {Vertical III-V/High-k Nanowire MOS Capacitors and Transistors},
  year         = {2016},
}